ICSSSTUB32872A Datasheet, PDF (18/18 Pages) Integrated Circuit Systems – 28-Bit Registered Buffer for DDR2

ICSSSTUB32872A
Advance Information
Revision History
Rev. Issue Date
A
5/2/2006
B 12/12/2006
C 12/20/2006
Description
Initial Release.
Electrical table, Ci Data input max changed from 3.5 to 5.0, CLK max
changed from 3 to 3.8
Timing table, ts Data before CK changed from 0.5 to 0.7, th DCS after CK
changed from 0.5 to 0.6
Page #
-
11
12
Applications, removed "800"; Electrical table, Idd Operating max changed
D
12/21/2006
from 80 to 150, Ci RESET typ changed from 2.5 to 4.5; Timing table, th Hold
Time, changed Q to Dn, Switching table, changed tpdm max from 1.7 to 1.9,
1, 11, 12
thl min from 1 to 0.9, and tpdmss max from 1.9 to 2.
E
3/6/2007
Timing table, ts Data before CK changed from 0.7 to 0.6; Switching table,
fixed typos.
12
Page 1, Recc. List, changed 3rd bullet to "Provides complete DDR DIMM
F
3/13/2007 solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A"; page 11, 1, 11
fixed typos.
1222F—3/13/07
18