ICSSSTUB32872A Datasheet, PDF (12/18 Pages) Integrated Circuit Systems – 28-Bit Registered Buffer for DDR2

ICSSSTUB32872A
Advance Information
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
VDD = 1.8V ±0.1V
MIN MAX
f_clock
t_W
t_ACT
Clock frequency
Pulse duration
Differential inputs active time
410
1
10
t_INACT Differential inputs inactive time
15
t_S
Setup time
Hold time
t_H
Hold time
Data before CK↑, CK↓
0.6
DCS0, DSC1 before CK↑,
CK↓, CSR high
0.7
DCS, DODT, DCKE and Dn
after CK↑, CK↓
0.6
PAR_IN after CK↑, CK↓
0.5
UNITS
MHz
ns
ns
ns
ns
ns
ns
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CK/CK signal input slew rate of 1V/ns.
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement Conditions
MIN
fmax Max input clock frequency
410
t_PDM
Propagation delay, single _{CK↑ and CK↓ to Qn}
bit switching
1.25
t_LH
Low to High propagation
delay
CK↑ and CK↓ to PTYERR
1.2
t_HL
High to low propagation
delay
0.9
t_PDMSS
Propagation delay
simultaneous switching
CK↑ and CK↓ to Qn
t_PHL
High to low propagation
delay
RESET ↓ to Qn↓
t_PLH
Low to High propagation
delay
RESET↓ to PTYERR↑
1. Guaranteed by design, not 100% tested in production.
MAX Units
MHz
1.9 ns
3
ns
3
ns
2
ns
3
ns
3
ns
1222F—3/13/07
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