ICSSSTUB32872A Datasheet, PDF (4/18 Pages) Integrated Circuit Systems – 28-Bit Registered Buffer for DDR2

ICSSSTUB32872A
Advance Information
Ball Assignment
Signal Group Signal Name
Type
Ungated inputs DCKE0, DCKE1, SSTL_18
DODT0, DODT1
Chip Select D0 ... D21
gated inputs
SSTL_18
Chip Select
inputs
DCS0 , DCS1
SSTL_18
Re-driven
outputs
Q0...Q21,
QCS0-1,
QCKE0-1,
QODT0-1
SSTL_18
Description
DRAM function pins not associated with Chip Select.
DRAM inputs, re-driven only when Chip Select is LOW.
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will be
low when a valid address/command is present. The register
can be programmed to re-drive all D-inputs when at least
one Chip Slect input is LOW.
Outputs of the register, valid after the specified clock count
and immediately following a rising edge of the clock.
Parity input PARIN
Parity error
output
PTYERR
Clock inputs CK, CK
Miscellaneous
inputs
RESET
VREF
SSTL_18
Open drain
Input parity is received on pin PARIN and should maintain
odd parity across the D0...D20 inputs, at the rising edge of the
clock.
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
PTYERR will be active for two clock cycles, and delayed by
an additional clock cycle for compatibility with final parity
out timing on the industry-standard DDR-II register with
parity (in JEDEC definition).
SSTL_18
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the positive
clock input (CK).
1.8 V
LVCMOS
Asynchronous reset input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET
also resets the PTYERR signal.
0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
1222F—3/13/07
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