ICS843034 Datasheet, PDF (6/23 Pages) Integrated Circuit Systems – MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843034
FEMTOCLOCKS™
MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
MR nP_LOAD M
Inputs
Conditions
N S_LOAD S_CLOCK S_DATA
H
X
XX
X
X
X Reset. Forces outputs LOW.
L
L
Data Data
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
↑
Data Data
L
L
H
XX
L
L
H
XX
↑
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
↑
Data
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
L
Data
Contents of the shift register are passed to the
M divider and N output divider.
L
H
XX
↓
L
Data M divider and N output divider values are latched.
L
H
XX
L
X
X Parallel or serial input do not affect shift registers.
L
H
XX
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
↑
Data S_DATA passed directly to M divider as it is clocked.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency
(MHz)
M Divide
256
M8
128
M7
64
M6
32
M5
16
M4
8
M3
4
M2
2
M1
1
M0
575
23
0
0
0
0
1
0
1
1
1
•
•
•
•
•
•
•
•
•
•
•
700
28
0
0
0
0
1
1
1
0
0
•
•
•
•
•
•
•
•
•
•
•
750
30
0
0
0
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of
25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
*NX2 *NX1 *NX0
N Divider Value
Output Frequency (MHz)
Minimum Maximum
0
0
0
1
560
750
0
0
1
2
280
375
0
1
0
3
186.66
250
0
1
1
4
140
187.5
1
0
0
5
112
150
1
0
1
6
93.33
125
1
1
0
8
70
93.75
1
1
1
16
35
46.875
*NOTE: X denotes Bank A or Bank B
843034AY
www.icst.com/products/hiperclocks.html
6
REV. A JULY 25, 2005