ICS843034 Datasheet, PDF (4/23 Pages) Integrated Circuit Systems – MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843034
FEMTOCLOCKS™
MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 41, 42,
43, 44,
45, 47, 48
2, 3
4
Name
M8, M0, M1,
M2, M3,
M4, M6, M7
NB0, NB1
NB2
5
OE_REF
6
OE_A
7
8, 14
9, 10
11
12, 24
13
OE_B
V_CC
NA0, NA1
NA2
V_EE
TEST
15, 16
17
18, 19
20
21
22
23
FOUTA0,
nFOUTA0
V_{CCO_A}
FOUTB0,
nFOUTB0
V_{CCO_B}
REF_CLK
V_{CCO_REF}
nc
25
MR
26
S_CLOCK
27
S_DATA
28
S_LOAD
29
30, 31
V_CCA
SEL0, SEL1
32
TEST_CLK
33, 34
35, 36
XTAL_IN0,
XTAL_OUT0
XTAL_IN1,
XTAL_OUT1
Continued on next page...
Type
Description
Input
Pulldown
M divider input. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS/LVTTL interface levels.
Input
Input
Input
Input
Input
Power
Input
Input
Power
Output
Output
Pullup _{Determines output divider value as defined in Table 3C,}
Pulldown ^{Function Table. LVCMOS/LVTTL interface levels.}
Pulldown
Pullup
Pullup
Output enable. Controls enabling and disabling of REF_CLK output.
LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTA0,
nFOUTA0 outputs. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTB0,
nFOUTB0 outputs. LVCMOS/LVTTL interface levels.
Core supply pins.
Pullup _{Determines output divider value as defined in Table 3C,}
Pulldown ^{Function Table. LVCMOS/LVTTL interface levels.}
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
LVCMOS/LVTTL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Power
Output supply pin for FOUTA0, nFOUTA0.
Output
Differential output for the synthesizer. LVPECL interface levels.
Power
Output
Power
Unused
Input
Input
Input
Input
Power
Pulldown
Pulldown
Pulldown
Pulldown
Output supply pin for FOUTB0, nFOUTB0.
Reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REF_CLK.
No connect.
Active High Master Reset. When logic HIGH, forces the internal
dividers are reset causing the true outputs FOUTx to go low and the
inverted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Assertion of MR does not
affect loaded M, N, and T values. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Input Pulldown Clock select inputs. LVCMOS/LVTTL interface levels.
Input
Input
Input
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN0 is the input,
XTAL_OUT0 is the output.
Crystal oscillator interface. XTAL_IN1 is the input,
XTAL_OUT1 is the output.
843034AY
www.icst.com/products/hiperclocks.html
4
REV. A JULY 25, 2005