ICS843034 Datasheet, PDF (18/23 Pages) Integrated Circuit Systems – MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843034
FEMTOCLOCKS™
MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
APPLICATION SCHEMATIC EXAMPLE
Figure 8 shows a schematic example of using an ICS843034.
In this example, the CLK/nCLK input is driven by a 3.3V
LVPECL driver. The data sheet also shows the CLK/nCLK
input driven by various types of drivers. The crystal inputs are
parallel resonant crystal with load capacitor CL=18pF. The
frequency fine tuning capacitors C1 and C2 are 22pF. This
schematic example shows hardwired logic control input
handling. The logic inputs can also be driven by 3.3V LVCMOS
drivers. It is recommended to have one decouple capacitor
per power pin. In general, the decoupling capacitor values
are ranged from 0.01uF to 0.1uF. Each decoupling capacitor
should be located as close as possible to the power pin. The
low pass filter R9, C11 and C16 for clean analog supply
should also be located as close to the VCCA pin as possible.
Only two examples of 3.3V LVPECL termination are shown in
this schematic example. Additional LVPECL terminations can
be found in the LVPECL Termination Application Note. The
data sheet also shows 2.5V LVPECL terminations. The
REF_CLK is LVCMOS driver with 7Ω output impedance. Series
termination for REF_CLK is shown in the example. Additional
LVCMOS termination can be found in the LVCMOS Application
Note. If the REF_CLK is not used, it is recommended to disable
this output by setting REF_OE to logic low. To disable
REF_CLK, REF_OE pin can be left floating (default logic low
by internal 51K pull down) or pull down using an external
1KΩ resistor.
3. 3V
Zo = 50
LVPECL
Zo = 50
R10
50
R 11
50
R12
50
VCC
C9
0. 1u
1
2
3
M8
NB0
4
5
6
NB1
NB2
OE_REF
7 ^OE_A
8
9
OE_B
VC C
10 ^NA0
11
12
NA1
NA2
VEE
VCC=3.3V
VCCO=3.3V
VCCO_REF=3.3V
VC C
C5
0.1u
VCCO
C7
0.1u
C8
0.1u
C1
X1
C2
22p CL=18pF 22p
C3
X1
C4
X_OUT1
X_IN1
36
35
34
X_OUT0
X_IN0
TEST_C LK
33
32
31
SEL1 ₃₀
SEL0
VC CA
29
28
S_LOAD ₂₇
S_D ATA
S_CLOCK
26
25
MR
22p CL=18pF 22p
VC CA
VC C
R9
10
U1
I CS843034
C11
C16
0.01u
10u
VCCO_REF
C6
0.1u
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R2
R1
50
50
R8 43 Zo = 50 Ohm
R3
50
LVC MOS
Logic Input Pin Examples
Set Logic
Set Logic
VCC Input to VCC Input to
'1'
'0'
RU1
1K
To Logic
Input
pins
RD1
SPARE
RU2
SPAR E
To Logic
Input
pins
RD2
1K
VCCO
R4
133
Zo = 50 Ohm
Zo = 50 Ohm
R5
Alternative
82.5
Termination
Exmaple
R6
133
+
-
R7
82.5
843034AY
FIGURE 8. ICS843034 APPLICATION SCHEMATIC EXAMPLE
www.icst.com/products/hiperclocks.html
18
REV. A JULY 25, 2005