ICS843034 Datasheet, PDF (16/23 Pages) Integrated Circuit Systems – MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843034
FEMTOCLOCKS™
MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS843034 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 5 below
were determined using a 18pF parallel resonant crystal and were
chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
X1
18pF Parallel Crystal
XTAL_OUT
C1
18p
XTAL_IN
C2
22p
843034
ICS84332
Figure 5. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUTx and nFOUTx are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 6A and 6B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Z_o = 50Ω
FIN
Z_o = 50Ω
84Ω
84Ω
FIGURE 6A. LVPECL OUTPUT TERMINATION
FIGURE 6B. LVPECL OUTPUT TERMINATION
843034AY
www.icst.com/products/hiperclocks.html
16
REV. A JULY 25, 2005