ICS843034 Datasheet, PDF (10/23 Pages) Integrated Circuit Systems – MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843034
FEMTOCLOCKS™
MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 7A. AC CHARACTERISTICS, V_CC = V_CCA = V_{CCO_A} = V_{CCO_B} = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
F_OUT
Output Frequency
tjit(Ø)
Phase Jitter, RMS (Random);
NOTE 1, 2
tjit(cc) Cycle-to-Cycle Jitter; NOTE 3, 4
tsk(o) Output Skew; NOTE 2, 4, 5
t_R / t_F
t_S
t_H
Output
Rise/Fall Time
Setup Time
Hold Time
LVPECL Outputs
REF_CLK
M, N to nP_LOAD
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
Test Conditions
333.33MHz,
Integration Range:
12kHz - 20MHz
Measured @ the same
Output Frequency
20% to 80%
Minimum Typical Maximum Units
35
750
MHz
0.80
ps
TBD
ps
50
ps
200
700
ps
5
ns
5
ns
5
ns
5
ns
5
ns
5
ns
odc
Output Duty Cycle
50
%
t_LOCK
PLL Lock Time
1
ms
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Characterized with REF_CLK output disabled.
NOTE 3: Jitter perforance using XTAL inputs.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
TABLE
7B.
AC
CHARACTERISTICS,
V=
CC
V=
CCA
3.3V±5%,
V
CCO_A
=
V
CCO_B
=
2.5V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum
F_OUT
tjit(Ø)
tjit(cc)
tsk(o)
t_R / t_F
Output Frequency
Phase Jitter, RMS (Random);
NOTE 1, 2
Cycle-to-Cycle Jitter; NOTE 3, 4
Output Skew; NOTE 2, 4, 5
Output
LVPECL Outputs
Rise/Fall Time _{REF_CLK}
35
333.33MHz,
Integration Range:
12kHz - 20MHz
Measured @ the same
Output Frequency
20% to 80%
200
M, N to nP_LOAD
5
t_S
Setup Time S_DATA to S_CLOCK
5
S_CLOCK to S_LOAD
5
M, N to nP_LOAD
5
t_H
Hold Time
S_DATA to S_CLOCK
5
S_CLOCK to S_LOAD
5
odc
Output Duty Cycle
t_LOCK
PLL Lock Time
For notes, see Table 7A above.
843034AY
www.icst.com/products/hiperclocks.html
Typical
TBD
TBD
50
50
Maximum Units
750
MHz
ps
ps
ps
700
ps
ns
ns
ns
ns
ns
ns
%
1
ms
REV. A JULY 25, 2005
10