ICS951413 Datasheet, PDF (15/23 Pages) Integrated Circuit Systems – Programmable System Clock Chip for ATI RS400 P4-based Systems

Integrated
Circuit
Systems, Inc.
ICS951413
Absolute Max
Symbol
Parameter
VDD_A
3.3V Core Supply Voltage
VDD_In 3.3V Logic Input Supply Voltage
Ts
Tambient
Tcase
ESD prot
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
0
2000
Max
V_DD + 0.5V
V_DD + 0.5V
150
70
115
Units
V
V
°_C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBO
L
CONDITIONS
Input High Voltage
V_IH
3.3 V +/-5%
Input Low Voltage
Input High Current
Input Low Current
V_IL
3.3 V +/-5%
I_IH
V_IN = V_DD
I_IL1
V_IN = 0 V; Inputs with no pull-
up resistors
I_IL2
V_IN = 0 V; Inputs with pull-up
resistors
MIN
2
V_SS - 0.3
-5
-5
-200
TYP
MAX UNITS Notes
V_DD + 0.3
V
1
0.8
V
1
5
uA
1
uA
1
uA
1
Low Threshold Input-
High Voltage
V_{IH_FS}
3.3 V +/-5%
0.7
V_DD + 0.3
V
1
Low Threshold Input-
Low Voltage
V_{IL_FS}
3.3 V +/-5%
V_SS - 0.3
0.35
Operating Current
I_DD3.3OP
all outputs driven
400
Powerdown Current
I_DD3.3PD
all diff pairs driven
all differential pairs tri-stated
70
12
Input Frequency
F_i
V_DD = 3.3 V
14.31818
Pin Inductance
L_pin
7
C_IN
Logic Inputs
5
Input Capacitance
C_OUT
Output pin capacitance
6
C_INX
X1 & X2 pins
5
Clk Stabilization
T_STAB
From V_DD Power-Up or de-
assertion of PD# to 1st clock
1.8
Modulation Frequency
Triangular Modulation
30
33
Tdrive_PD#
CPU output enable after
300
PD# de-assertion
Tfall_Pd#
PD# fall time of
5
Trise_Pd#
PD# rise time of
5
SMBus Voltage
V_DD
2.7
5.5
Low-level Output Voltage V_OL
@ I_PULLUP
Current sinking at
V_OL = 0.4 V
I_PULLUP
4
SCLK/SDATA
Clock/Data Rise Time
T_RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
0.4
1000
SCLK/SDATA
(Min VIH + 0.15) to
Clock/Data Fall Time
T_FI2C
(Max VIL - 0.15)
300
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet}
ppm frequency accuracy on PLL outputs.
V
1
mA
1
mA
1
mA
1
MHz 3
nH
1
pF
1
pF
1
pF
1
ms 1,2
kHz
1
us
1
ns
1
ns
2
V
1
V
1
mA
1
ns
1
ns
1
0929C—03/07/05
15