ICS951413 Datasheet, PDF (13/23 Pages) Integrated Circuit Systems – Programmable System Clock Chip for ATI RS400 P4-based Systems

Integrated
Circuit
Systems, Inc.
ICS951413
SMBus Table: CPU Spread Spectrum Control Register
Byte 14 Pin #
Name
Control Function
Bit 7
-
Reserved
Reserved
Bit 6
-
SSP14
Bit 5
-
SSP13
Bit 4
-
Bit 3
-
Bit 2
-
SSP12
SSP11
SSP10
Spread Spectrum
Programming bit(14:8)
Bit 1
-
SSP9
Bit 0
-
SSP8
Type
0
1
R
-
-
RW
RW
RW
These Spread Spectrum
bits in Byte 13 and 14 will
RW
program the spread
RW
pecentage of CPU
RW
RW
PWD
0
X
X
X
X
X
X
X
SMBus Table: SRC Frequency Control Register
Byte 15 Pin #
Name
Control Function Type
0
1
Bit 7
-
N Div8
N Divider Prog bit 8 RW
The decimal
Bit 6
-
N Div9
N Divider Prog bit 9 RW representation of M and
Bit 5
-
M Div5
RW N Divier in Byte 15 and
Bit 4
-
Bit 3
-
Bit 2
-
M Div4
M Div3
M Div2
RW 16 will configure the SRC
M Divider Programming RW VCO frequency. Default
bits
RW at power up = latch-in or
Bit 1
-
M Div1
RW Byte 0 Rom table. VCO
Bit 0
-
M Div0
RW Frequency = 14.318 x
PWD
X
X
X
X
X
X
X
X
SMBus Table: SRC Frequency Control Register
Byte 16 Pin #
Name
Control Function
Bit 7
-
N Div7
Bit 6
-
N Div6
Bit 5
-
Bit 4
-
Bit 3
-
N Div5
N Div4
N Div3
N Divider Programming
b(7:0)
Bit 2
-
N Div2
Bit 1
-
N Div1
Bit 0
-
N Div0
Type
0
1
RW
The decimal
RW representation of M and
RW N Divier in Byte 15 and
RW 16 will configure the SRC
RW VCO frequency. Default
RW at power up = latch-in or
RW Byte 0 Rom table. VCO
RW Frequency = 14.318 x
PWD
X
X
X
X
X
X
X
X
SMBus Table: SRC Spread Spectrum Control Register
Byte 17 Pin #
Name
Control Function
Bit 7
-
SSP7
Bit 6
-
SSP6
Bit 5
-
Bit 4
-
Bit 3
-
SSP5
SSP4
SSP3
Spread Spectrum
Programming b(7:0)
Bit 2
-
SSP2
Bit 1
-
SSP1
Bit 0
-
SSP0
Type
0
1
RW
RW
RW These Spread Spectrum
RW bits in Byte 17 and 18 will
RW program the spread
RW pecentage of SRC
RW
RW
PWD
X
X
X
X
X
X
X
X
0929C—03/07/05
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