ICS951413 Datasheet, PDF (11/23 Pages) Integrated Circuit Systems – Programmable System Clock Chip for ATI RS400 P4-based Systems

Integrated
Circuit
Systems, Inc.
ICS951413
SMBus Table: Device ID Register
Byte 6 Pin #
Name
Bit 7
-
DevID 7
Bit 6
-
DevID 6
Bit 5
-
DevID 5
Bit 4
-
DevID 4
Bit 3
-
DevID 3
Bit 2
-
DevID 2
Bit 1
-
DevID 1
Bit 0
-
DevID 0
Control Function Type
0
Device ID MSB
R
-
Device ID 6
R
-
Device ID 5
R
-
Device ID4
R
-
Device ID3
R
-
Device ID2
R
-
Device ID1
R
-
Device ID LSB
R
-
1
PWD
-
0
-
0
-
0
-
1
-
0
-
0
-
1
-
1
SMBus Table: Vendor ID Register
Byte 7 Pin #
Name
Bit 7
-
RID3
Bit 6
-
RID2
Bit 5
-
RID1
Bit 4
-
RID0
Bit 3
-
VID3
Bit 2
-
VID2
Bit 1
-
VID1
Bit 0
-
VID0
Control Function Type
0
Revision ID
R
-
Starts at 0 hex for A ^R
-
revsion.
R
-
R
-
R
-
VENDOR ID
R
-
(0001 = ICS)
R
-
R
-
1
PWD
-
X
-
X
-
X
-
X
-
0
-
0
-
0
-
1
SMBus Table: Byte Count Register
Byte 8 Pin #
Name
Bit 7
-
BC7
Bit 6
-
BC6
Bit 5
-
BC5
Bit 4
-
BC4
Bit 3
-
BC3
Bit 2
-
BC2
Bit 1
-
BC1
Bit 0
-
BC0
Control Function
Byte Count
Programming b(7:0)
Type
0
1
RW
RW
RW Writing to this register will
RW configure how many
RW bytes will be read back,
RW
default is 9 bytes.
RW
RW
PWD
0
0
0
0
1
0
0
1
SMBus Table: WD TimeR Control Register
Byte 9 Pin #
Name
Control Function
Bit 7
-
WDH_EN
Watchdog Hard Alarm
Enable
Bit 6
-
WDS_EN
Watchdog Soft Alarm
Enable
Bit 5
-
WD Hard Status WD Hard Alarm Status
Bit 4
-
WD Soft Status WD Soft Alarm Status
Bit 3
-
WDTCtrl
Watch Dog Time base
Control
Bit 2
-
WD2
WD Timer Bit 2
Bit 1
-
WD1
WD Timer Bit 1
Bit 0
-
WD0
WD Timer Bit 0
Type
0
RW Disable
1
Enable
RW Disable
Enable
R Normal
Alarm
R Normal
Alarm
RW 290ms Base ^1160ms
Base
RW ^{These bits represent}
X*290ms (or 1.16S) the
RW
watchdog timer waits
before it goes to alarm
mode. Default is 7 X
RW
290ms = 2s.
0929C—03/07/05
PWD
0
0
X
X
0
1
1
1
11