ICS951413 Datasheet, PDF (12/23 Pages) Integrated Circuit Systems – Programmable System Clock Chip for ATI RS400 P4-based Systems

Integrated
Circuit
Systems, Inc.
ICS951413
SMBus Table: M/N Programming & WD Safe Frequency Control Register
Byte 10 Pin #
Name
Control Function Type
0
1
Bit 7
-
M/N_EN
PLLS M/N Programming
Enable
RW
Disable
Enable
Bit 6
-
Reserved
Reserved
RW
-
-
Bit 5
-
WD Safe Freq
Source
WD Safe Freq Source RW B10b(4:0)
Latch
Inputs
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Watch Dog Safe Freq
Programming bits
RW
RW
RW
Writing to these bit will
configure the safe
frequency as Byte0 bit
RW
(4:0).
RW
PWD
0
0
0
0
0
0
0
0
SMBus Table: CPU Frequency Control Register
Byte 11 Pin #
Name
Control Function Type
0
1
Bit 7
-
N Div8
N Divider Prog bit 8 RW
The decimal
Bit 6
-
N Div9
N Divider Prog bit 9 RW representation of M and
Bit 5
-
M Div5
RW N Divier in Byte 11 and
Bit 4
-
Bit 3
-
Bit 2
-
M Div4
M Div3
M Div2
RW 12 will configure the CPU
M Divider Programming RW VCO frequency. Default
bit (5:0)
RW at power up = latch-in or
Bit 1
-
M Div1
RW Byte 0 Rom table. VCO
Bit 0
-
M Div0
RW Frequency = 14.318 x
PWD
X
X
X
X
X
X
X
X
SMBus Table: CPU Frequency Control Register
Byte 12 Pin #
Name
Control Function Type
0
1
Bit 7
-
N Div7
RW
The decimal
Bit 6
-
N Div6
RW representation of M and
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
N Div5
N Div4
N Div3
N Div2
N Divider Programming
Byte12 bit(7:0) and
Byte11 bit(7:6)
RW N Divier in Byte 11 and
RW 12 will configure the CPU
RW VCO frequency. Default
RW at power up = latch-in or
Bit 1
-
N Div1
RW Byte 0 Rom table. VCO
Bit 0
-
N Div0
RW Frequency = 14.318 x
PWD
X
X
X
X
X
X
X
X
SMBus Table: CPU Spread Spectrum Control Register
Byte 13 Pin #
Name
Control Function
Bit 7
-
SSP7
Bit 6
-
SSP6
Bit 5
-
SSP5
Bit 4
-
SSP4
Spread Spectrum
Bit 3
-
SSP3
Programming bit(7:0)
Bit 2
-
SSP2
Bit 1
-
SSP1
Bit 0
-
SSP0
Type
0
1
RW
RW
RW These Spread Spectrum
RW bits in Byte 13 and 14 will
RW program the spread
RW pecentage of CPU
RW
RW
PWD
X
X
X
X
X
X
X
X
0929C—03/07/05
12