ICS951413 Datasheet, PDF (10/23 Pages) Integrated Circuit Systems – Programmable System Clock Chip for ATI RS400 P4-based Systems

Integrated
Circuit
Systems, Inc.
ICS951413
SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register
Byte 3 Pin #
Name
Control Function Type
Bit 7
12,13
SRCCLK7
RW
Bit 6
16,17
SRCCLK6
Master Output control. RW
Bit 5
18,19
SRCCLK5
Enables or disables RW
Bit 4
22,23
SRCCLK4
output, regardless of RW
Bit 3
24,25
SRCCLK3
CLKREQ# inputs. RW
Bit 2
34,33
SRCCLK0
RW
Bit 1
24,25
REQASRC3
CLKREQA# Controls _RW
SRC3
Bit 0
34,33
REQASRC0
CLKREQA# Controls
SRC0
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Does not
control
Does not
control
1
Enable
Enable
Enable
Enable
Enable
Enable
Controls
Controls
PWD
1
1
1
1
1
1
0
0
SMBus Table: SRCCLK(3,0), ATIGCLK Output Control Register
Byte 4 Pin #
Name
Control Function Type
Bit 7
12,13
REQASRC7
CLKREQA# Controls
SRC7
RW
Bit 6
16,17
REQASRC6
CLKREQA# Controls _RW
SRC6
Bit 5
18,19
REQASRC5
CLKREQA# Controls _RW
SRC5
Bit 4
22,23
REQASRC4
CLKREQA# Controls _RW
SRC4
Bit 3
27,28
ATIGCLK1
Output Enable
These outputs cannot be ^RW
Bit 2
30,29
ATIGCLK0
controlled by CLKREQ#
pins.
RW
0
Does not
control
Does not
control
Does not
control
Does not
control
Disabled
Disabled
CPU, SRC, Differential Output Hi-Z or driven when
Bit 1
ATIG
Disable Mode
disabled
RW
Driven
Bit 0
4
USB_48Str 48MHz Strength Control RW
1X
1
Controls
Controls
Controls
Controls
Enabled
Enabled
Hi-Z
2X
PWD
0
0
0
0
1
1
0
1
NOTE: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output.
Behavior of the device is undefined under these conditions.
SMBus Table: Output Drive and ATIG Frequency Control Register
Byte 5 Pin #
Name
Control Function Type
0
1
Bit 7
52
REF2Str
REF2 Strength Control RW
1X
2X
Bit 6
Bit 5
41,40
43,42
CPU2_Stop_En ^{0 = CPU is free-run} RW
1 = CPU is stopped by
CPU1_Stop_En
CPU_STOP#
RW
Free-Run
Free-Run
Stoppable
Stoppable
Bit 4
-
SRCFS4
(SS_EN)
Freq Select Bit 4
(SS_EN)
RW
Bit 3
-
Bit 2
-
SRCFS3
SRCFS2
Freq Select Bit 3
Freq Select Bit 2
RW
See Table 2 SRC
RW Frequency Selection
Bit 1
-
SRCFS1
Freq Select Bit 1 RW
Bit 0
-
SRCFS0
Freq Select Bit 0 RW
NOTE: CPU(1:2)_Stop_En (Byte5, bit 6:5) only exist in devices with REV ID = 2 or higher
0929C—03/07/05
PWD
1
1
1
0
0
0
0
0
10