IC43R32400 Datasheet, PDF (7/18 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM

IC43R32400
Mode Register Set (MRS)
The mode register is divided into various fields depending on functionality.
Burst Length Field (A2, A1, A0)
This field specifies the data length of column access and selects the Burst Length.
Addressing Mode Select Field (A3)
The Addressing Mode can be Interleave Mode or Sequential Mode. Both Sequential Mode and
Interleave Mode support burst length of 2, 4 and 8. Full page burst length is only for Sequential mode.
CAS# Latency Field (A6, A5, A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first read
data. The minimum whole value of CAS# Latency depends on the frequency of CK. The minimum whole
value satisfying the following formula must be programmed into this field.
tCAC(min) _ CAS# Latency X tCK
Test Mode field :A7; DLL Reset Mode field : A8
These two bits must be programmed to “00” in normal operation.
( BA0, BA1)
Mode Resistor Bitmap
Brst Definition, Addressing Sequence of Sequential and Interleave Mode
Burst Length Start Address
A2 A1 A0
2
XX0
XX1
X
0
0
4
X
0
1
Sequential
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
Interleave
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
X
10
2, 3, 0, 1
2, 3, 0, 1
X
11
3, 0, 1, 2
3, 2, 1, 0
0
00
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
0
01
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
0
10
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
8
0
11
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
1
00
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1
01
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
1
10
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
1
11
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Integrated Circuit Solution Inc.
7
DDR003-0B 11/10/2004