IC43R32400 Datasheet, PDF (6/18 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM

IC43R32400
VSS
VDDQ
VSSQ
VREF
NC
Supply
Supply
Supply
Supply
-
Ground: Ground for the input buffers and core logic.
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Reference Voltage for Inputs: +0.5 x VDDQ
No Connect: These pins should be left unconnected.
Note: The timing reference point for the differential clocking is the cross point of the CK and CK#. For any applications
using the single ended clocking, apply VREF to CK# pin.
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 2 shows the
truth table for the operation commands.
Command
Table 2. Truth Table (Note (1), (2) )
State CKEn-1 CKEn DM BA1
BankActivate
Idle ⁽³⁾
H
X
X
V
BankPrecharge
Any
H
X
X
V
PrechargeAll
Any
H
X
X
X
Write
Active ⁽³⁾
H
X
V
V
Write and Auto Precharge Active ⁽³⁾ H
X
V
V
Read
Active ⁽³⁾
H
X
X
V
Read and Autoprecharge Active ⁽³⁾ H
X
X
V
Mode Register Set
Idle
H
X
X
L
Extended Mode Register Set Idle
H
X
X
L
No-Operation
Any
H
X
X
X
Device Deselect
Any
H
X
X
X
Burst Stop
Any⁽⁴⁾
H
X
X
X
AutoRefresh
Idle
H
H
X
X
SelfRefresh Entry
Idle
H
L
X
X
SelfRefresh Exit
Idle
L
H
X
X
(SelfRefresh)
Power Down Mode Entry Idle/Active⁽⁵⁾ H
L
X
X
Power Down Mode Exit Any
L
H
X
X
(PowerDown)
Data Write/Output Enable Active
H
X
L
X
Data Mask/Output Disable Active
H
X
H
X
BA0 A8 A11-A9,A7-0 CS#
V Row address L
VL
XL
XH
XL
VL
VH
Column L
address _L
A0~A7
VL
VH
Column ^L
address _L
A0~A7
L OP code
L
H OP code
L
XX
X
L
XX
X
H
XX
X
L
XX
X
L
XX
X
L
XX
X
H
L
XX
X
H
L
XX
X
H
L
XX
X
X
XX
X
X
RAS# CAS# WE#
L
H
H
L
H
L
L
H
L
H
L
L
H
L
L
H
L
H
H
L
H
L
L
L
L
L
L
H
H
H
X
X
X
H
H
L
L
L
H
L
L
H
X
X
X
H
H
H
X
X
X
H
H
H
X
X
X
HH
H
X
X
X
X
X
X
Note:
1. V =Valid Data, X =Don ’t care,L =Low level, H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA1 signals.
4. Read burst stop with BST command for all burst types.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle,device state is clock suspend mode.
6
Integrated Circuit Solution Inc.
DDR003-0B 11/10/2004