IC43R32400 Datasheet, PDF (12/18 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM

IC43R32400
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 2.5V +/- 5%, Ta = 0~70 _°C)
Symbol
Parameter
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tDS
tDH
CL = 3
Clock cycle time
CL = 4
CL = 5
Clock high level width
Clock low level width
DQS-out access time from CK,CK#
Output access time from CK,CK#
DQS-DQ Skew
Read preamble
Read postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS write postamble
DQS in high level pulse width
DQS in low level pulse width
Address and Control input setup time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tHP
Clock half period
tQH
Output DQS valid window
4.0
Min Man
4
10
5.0 Unit
Min Max
5 10 ns
4
10
5
10
4
5
0.45 0.55
0.45 0.55
-0.7 0.7
-0.7 0.7
-
0.4
0.9 1.1
0.4 0.6
0.85 1.15
0
-
0.35 -
0.4 0.6
0.4 0.6
0.4 0.6
0.9 -
0.45 -
0.45 -
5 10
0.45 0.55 tCK
0.45 0.55 tCK
-0.7 0.7 ns
-0.7 0.7 ns
-
0.45 ns
0.9 1.1 tCK
0.4 0.6 tCK
0.85 1.15 tCK
0 - ns
0.35 - ns
0.4 0.6 tCK
0.4 0.6 tCK
0.4 0.6 tCK
1.0 - ns
0.5 - ns
0.5 - ns
tCLMIN
or
-
tCLMIN
or - ns
tCHMIN
tCHMIN
tHP- -
tHP - -
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tRRD
twR
tCDLR
tCCD
tMRD
tDAL
tXSA
Row cycle time
Refresh row cycle time
Row active time
RAS# to CAS# Delay in Read
RAS# to CAS# Delay in Write
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. Address to Col. Address delay
Mode register set cycle time
Auto precharge write recovery + Precharge
Self refresh exit to read command delay
tPDEX Power down exit time
0.45
0.5
ns
15 -
12 - tCK
17 -
14 - tCK
10
100K
8 100K tCK
5
-
4
- tCK
3
-
2
- tCK
3
-
3
- tCK
3
-
2
- tCK
3
-
2
- tCK
2
-
2
- tCK
1
-
1
- tCK
2
-
2
- tCK
8
-
7
- tCK
200 -
200
- tCK
tIS + 2tCK -
tIS + 2tCK -
ns
tREF
Refresh interval time
-
7.8
7.8 us
12
Integrated Circuit Solution Inc.
DDR003-0B 11/10/2004