IC43R32400 Datasheet, PDF (11/18 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM

IC43R32400
Decoupling Capacitance Guide Line
Symbol
CDC1
CDC2
Parameter
Decouping Capacitance between VDD and VSS
Decouping Capacitance between VDDQ and VSSQ
AC Input Operating Conditions
(VDD = 2.5V +/- 5%, Ta = 0~70 _°C)
Symbol
Parameter
VIH
Input High Voltage; DQ
VIL
Input Low Voltage; DQ
VID
Clock Input Differential Voltage; Ck & CK#
VIX
Clock Input Crossing Point Voltage; Ck & CK#
Value
Unit
0.1+0.01
uF
0.1+0.01
uF
Min
VREF+0.4
-
0.8
0.5xVDDQ-0.2
Max
Unit
-
V
VREF-0.4
V
VDDQ+0.6
V
0.5xVDDQ+0.2
V
AC Operating Test Conditions
(VDD = 2.5V +/- 5%, Ta = 0~70 _°C)
Reference Level of Output Signals (VRFE)
CK & CK# signal maximum peak swing
Output Load
Input Signal Levels
Input Signals Slew Rate
Input timing measurement reference level
Output timing measurement reference level
Reference Level of Input Signals
0.5 x VDDQ
1.5V
See Figure. A Test Load
VREF+0.4 V / VREF-0.4 V
1 V/ns
VREF
VTT
0.5 x VDDQ
Fiaure A. Test Load
Integrated Circuit Solution Inc.
11
DDR003-0B 11/10/2004