IC43R32400 Datasheet, PDF (2/18 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM

IC43R32400
1M Words x 32 Bits x 4 Banks (128-MBIT)
DDR SYNCHRONOUS DYNAMIC RAM
FEATURES
Fast clock rate: 250/200 MHz
Differential Clock CK & CK# input
* _{4 Bi-directional DQS. Data transactions on both}
edges of DQS (1DQS / Byte)
DLL aligns DQ and DQS transitions
Edge aligned data & DQS output
Center aligned data & DQS input
4 internal banks, 1M x 32-bit for each bank
Programmable mode and extended mode registers
- CAS# Latency: 3, 4, 5
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleave
Full page burst length for sequential type only
Start address of full page burst should be even
All inputs except DQ’s & DM are at the positive
edge of the system clock
No Write-Interrupted by Read function
4 individual DM control for write masking only
Auto Refresh and Self Refresh
4096 refresh cycles / 32ms
Power supplies up to 250/200MHz:
VDD = 2.5V +/- 5%
VDDQ = 2.5V +/- 5%
Interface : SSTL_2 I/O compatible
Standard 144-ball FBGA package
Support Green Package
Overview
The IC43R32400 DDR SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 128
Mbits. It is internally configured as a quad 1M x 32 DRAM
with a synchronous interface (all signals are registered
on the positive edge of the clock signal, CK).
Data outputs occur at both rising edges of CK and CK#.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence.
Accesses begin with the registration of a BankActivate
command, which is then followed by a Read or Write
command.
The IC43R32400 provides programmable Read or Write
burst lengths of 2, 4, 8. An auto precharge function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The refresh functions, either Auto or Self Refresh are
easy to use.
In addition, IC43R32400 features programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications requiring
high memory bandwidth, result in a device particularly
well suited to high performance main memory and
graphics applications.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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Integrated Circuit Solution Inc.
DDR003-0B 11/10/2004