IC42S81600 Datasheet, PDF (5/69 Pages) Integrated Circuit Solution Inc – 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM

IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
PIN FUNCTIONS
Symbol
CLK
CKE
Type
Input Pin
Input Pin
CS
Input Pin
RAS, CAS, WE
A0-A11
Input Pin
Input Pin
BA0,BA1
DQM, UDQM ,LDQM
Input Pin
Input Pin
DQ0 to DQ15
VDD, VSS
VDDQ, VSSQ
I/O Pin
Power Supply Pin
Power Supply Pin
Function (In Detail)
Master Clock: Other inputs signals are referenecd to the CLK rising edge
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal
clock signals,device input buffers and output drivers. Deactivating the clock
provides PRECHARGE POWER-DOWN and SELF REFRESH operation
(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank).
Chip Select: CS enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS is registered
HIGH. CS provides for external bank selection on systems with multiple
banks. CS is considered part of the command code.
Command Inputs: RAS, CAS and WE (along with CS) define the command
being entered.
Address Inputs: Provide the row address for ACTIVE commands, and the
column address and AUTO PRECHARGE bit for READ/WRITE
commands, to select one location out of the memory array in the respective
bank. The row address is specified by A0-A11. The column address is
specified by A0-A9 (IC42S81600) / A0-A8 (IC42S16800)
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
Din Mask / Output Disable: When DQM is high in burst write, Din for the
current cycle is masked. When DQM is is high in burst read, Dout is
disable at the next but one cycle.
Data Input / Output: Data bus.
Power Supply for the memory array and peripheral circuitry.
Power Supply are supplied to the output buffers only.
Integrated Circuit Solution Inc.
5
DR023-0E 6/11/2004