IC42S81600 Datasheet, PDF (28/69 Pages) Integrated Circuit Solution Inc – 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM

IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask
invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid
data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be
high at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
CLK
Command
CAS latency = 2
DQM
DQ
command
CAS latency = 3
DQM
DQ
Burst lengh = X
T0
T1
T2
T3
T4
T5
T6
T7
T8
Write
PRE
ACT
D0
D1
D2
Write
D3
D4
t_RP
PRE
Hi - Z
ACT
D0
D1
D2
D3
D4
Hi - Z
t_RP
28
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004