IC42S81600 Datasheet, PDF (23/69 Pages) Integrated Circuit Solution Inc – 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM

IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
Read / Write Command Interval
Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previous
read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
CLK
Command
Burst lengh=4, CAS latency=2
T0
T1
T2
T3
T4
T5
T6
T7
T8
Read A
Read B
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminate and the new burst will begin
with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
CLK
Command
Burst lengh=4, CAS latency=2
T0
T1
T2
T3
T4
T5
T6
T7
T8
Write A
Write B
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
Integrated Circuit Solution Inc.
23
DR023-0E 6/11/2004