IC-MH8_14 Datasheet, PDF (5/25 Pages) IC-Haus GmbH – 12 BIT ANGULAR HALL ENCODER

iC-MH8
12 BIT ANGULAR HALL ENCODER
preliminary
Rev A1, Page 5/25
ELECTRICAL CHARACTERISTICS
Operating conditions:
VPA, VPD = 5 V ±10 %, VNA=VND, Tj = -40...125 ^◦C, IBM adjusted to 200 µA , 4 mm NdFeB magnet, unless otherwise noted
Item Symbol Parameter
No.
Conditions
Min. Typ. Max.
General
001 V(VPA), Permissible Supply Voltage
V(VPD)
4.5
5.5
002 I(VPA)
Supply Current in VPA
3
12
003 I(VPD) Supply Current in VPD
PRM = ’0’, without Load
5
27
004 I(VPD) Supply Current in VPD
PRM = ’1’, without Load
2
20
005 Vc()hi
Clamp Voltage hi at MA, SLI,
SLO, PTE, NERR
Vc()hi = V() − VPD, I() = 1 mA
0.4
1.5
006 Vc()lo
Clamp Voltage lo at MA, SLI,
SLO, PTE, NERR
I() = -1 mA
-1.5
-0.3
Hall Sensors and Signal Conditioning
101 Hext
Operating Magnetic Field
Strength
at surface of chip
20
100
102 fmag
Operating Magnetic Field
Frequency
Rotating Speed of Magnet
2
120 000
104 xdis
Max. Magnet Axis Displacement
0.2
vs. Center of Hall Sensor Array
108 Vos
Trimming range of output offset VOSS or VOSC = 0x7F
-55
voltage
109 Vos
Trimming range of output offset VOSS or VOSC = 0x3F
55
voltage
110 Vopt
Optimal differential output voltage Vopt = Vpp(PSIN) − Vpp(NSIN), ENAC = ’0’,
4
see Fig. 6
111 Vratio
Amplitude Ratio
Vratio = Vpp(PSIN) / Vpp(PCOS), GCC = 0x3F 1.09
Unit
V
mA
mA
mA
V
V
kA/m
kHz
rpm
mm
mV
mV
Vpp
112 Vratio
Amplitude Ratio
Vratio = Vpp(PSIN) / Vpp(PCOS), GCC = 0x40
0.92
Signal Level Control
201 Vpp
Differential Peak-to-Peak Output Vpp = Vpk(Px) − Vpk(Nx), ENAC = ’1’, see Fig.
Amplitude
6
202 ton
Controller Settling Time
to ±10% of final amplitude
203 Vt()lo
MINERR Amplitude Error Thresh- see 201
old
204 Vt()hi
MAXERR Amplitude Error
Threshold
see 201
Bandgap Reference
401 Vbg
Bandgap Reference Voltage
402 Vref
Reference Voltage
403 Iibm
Bias Current
CIBM = 0x0
CIBM = 0xF
Bias Current adjusted
404 VPDon
Turn-on Threshold VPD, System V(VPD) − V(VND), increasing voltage
on
405 VPDoff
Turn-off Threshold VPD, System V(VPD) − V(VND), decreasing voltage
reset
406 VPDhys Hysteresis System on/reset
407 Vosr
Reference voltage offset com-
pensation
Clock Generation
501 f()sys
System Clock
Bias Current adjusted
502 f()sdc
Sinus/Digital-Converter Clock Bias Current adjusted
3.2
1.0
4.8
1.18
45
-370
-220
3.65
3
0.3
475
0.85
13.5
1.25
50
-200
4.0
3.5
500
1.0
16
4.8 Vpp
300
µs
2.8 Vpp
5.8 Vpp
1.32
55
-100
-180
4.3
V
%VPA
µA
µA
µA
V
3.8
V
V
525 mV
1.2 MHz
18 MHz