IC-MH8_14 Datasheet, PDF (23/25 Pages) IC-Haus GmbH – 12 BIT ANGULAR HALL ENCODER

iC-MH8
12 BIT ANGULAR HALL ENCODER
preliminary
Rev A1, Page 23/25
forced by applying V(VZAP) = V()ZAP before chang-
ing the value of Bit ENSSI to avoid an aborted register
communication.
In the SSI mode the absolute position is output with 13
bits according to the SSI standard. (The data is trans-
mitted as Gray code with trailing zeros.)
Figure 25: SSI protocol, data GRAY-coded
The register range 0x00 to 0x0F is equivalent to the
settings with which the IC can be parameterised. The
settings directly affect the corresponding switching
parts. The range 0x10 to 0x1F is read-only and reflects
the contents of the integrated zapping diodes. Follow-
ing programming the data can be verified via these ad-
dresses. After the supply voltage is connected, the
contents of the zapping diodes are copied to the RAM
area 0x00 to 0x0F. Then the settings can be overwrit-
ten via the serial interface. Overwriting is not possible
if the CFGPROT bit is set.
With the profile ID, the data format can be requested
for the following sensor data cycles in the module. A
read operation at address 0x42 results in 0x2C, with is
the equivalent to 12-bit single-cycle data.
The status register provides information on the status
of the module. There are 5 different errors that can
be signaled. Following unsuccessful programming of
the zapping diodes, the bit PROGERR is set. If an
attempt is made to read the current position via the se-
rial interface during the start-up phase, an error is sig-
naled with ERRSDATA, as the actual position is not yet
known. The ERRAMAX bit is output to signal that the
amplitude is too high, while the ERRAMIN bit signals
an amplitude which is too low, caused, for example, by
too great a distance to the magnet. If the NERR pin
is pulled against VND outside the module, this error is
also signaled via the serial interface. The ERREXT bit
is then equal to ’1’. The error bits are reset again after
the status register is read out at the address 0x77. The
error bit in the data word is then also read in the next
cycle as ’0’.
CFGTOS
0
1
x
CFGTOB
0
0
1
Timeout
16 µs
2 µs
2 µs
Errors in the module are signaled via the error mes-
sage output NERR. This open-drain output signals an
error if the output is pulled against VND. If the er-
ror condition no longer exists, then the pin is released
again after a waiting time of approximately 1 ms. If the
integrated pull-up resistor is deactivated with DPU =
’1’, then an external resistor must be provided. With
DPU = ’0’ it brings the pin up to the high level again.
DPU
0
1
Addr. 0x04; bit 6
Pull-up activated
Pull-up deactivated
Table 29: Activation of NERR pull-up
Table 30: Timeout for sensor data
The timeout can be programmed to a shorter value
with the CFGTOS bit. However, this setting is reset
to the default value 16 µs again following a reset. The
timeout can be permanently programmed for faster
data transmission with the CFGTOB register via a zap-
ping diode. Resetting to slower data transmission is
then not possible.
The registers 0x7D to 0x7F are reserved for the man-
ufacturer and can be provided with an ID so that the
manufacturer can identify its modules
OTP Programming
CFGPROT
0
1
Addr. 0x05; bit 6
no protection
write/read protection
Table 31: Write/read protection of configuration
ENHC
0
1
Addr. 0x0f; bit 7
Default setting
ZAP diode testing: Use a higher current for reading
the ZAP diodes memory (0x10-0x1f)
Table 32: Enable High Current
With CFGPROT = ’0’, the registers at the addresses
0x00 to 0x0F and 0x78 to 0x7F are readable and write-