IC-MH8_14 Datasheet, PDF (22/25 Pages) IC-Haus GmbH – 12 BIT ANGULAR HALL ENCODER

iC-MH8
12 BIT ANGULAR HALL ENCODER
preliminary
Rev A1, Page 22/25
The property of the RS422 driver of the connected line
can be adjusted in the CFGDR register.
CFGDR(1:0)
Addr. 0x05; bit 1:0
00
10 MHz 4 mA (default)
01
10 MHz 50 mA
10
300 kHz 50 mA
11
3 MHz 20 mA
Table 25: Driver property
Signals with the highest frequency can be transmitted
in the setting CFGDR = ’00’. The driver capability is
at least 4 mA, however it is not designed for a 100 Ω
line. This mode is ideal for connection to a digital in-
put on the same assembly. With the setting CFGDR =
’01’ the same transmission speed is available and the
driver power is sufficient for the connection of a line
over a short distance. Steep edges on the output en-
able a high transmission rate. A lower slew rate is of-
fered by the setting CFGDR = ’10’, which is excellent
for longer lines in an electromagnetically sensitive en-
vironment. Use of the setting CFGDR = ’11’ is advis-
able at medium transmission rates with a limited driver
capability.
TRIHL
00
01
10
11
Addr. 0x05; bit 3:2
Push Pull Output Stage
Highside Driver
Lowside Driver
Tristate
Table 26: Tristate Register
The drivers consist of a push-pull stage in each case
with low-side and high-side drivers which can each be
activated individually. As a result, open-drain outputs
with an external pull-up resistor can also be realized.
Serial Interface
The serial interface is used to read out the absolute tailed description of the protocol, see separate inter-
position and to parameterise the module. For a de- face specification.
MA
SLI
SLO
CDM
Ack Start CDS D11 D10
D0 nE nW CRC5 CRC4
Data Range
Figure 24: Serial Interface Protocol
CRC0 Stop
Timeout
The sensor sends a fixed cycle-start sequence con-
taining the Acknowledge-, Start and Control-Bit fol-
lowed by the binary 12 bit sensor data. The low-active
error bit nE a ’0’ indicates an error which can be fur-
ther identified by reading the status register 0x77. The
following bit nW is always at ’1’ state. Following the
6 CRC bits the data of the next sensors, if available,
are presented. Otherwise, the master stops generat-
ing clock pulse on the MA line an the sensor runs into
a timeout, indicating the end of communication.
Serial Interface
Protocol
Cycle start sequence
Length of sensor data
CRC Polynome
CRC Mode
Multi Cycle Data
max. Data Rate
Mode C
Ack/Start/CDS
12 Bit + ERR + WARN
0b1000011
inverted
not available
10 MHz
Table 27: Interface Protocol
ENSSI
0
1
Addr. 0x05; bit 7
Extended SSI-Mode
SSI-Mode
Table 28: Activation of SSI mode
The extended SSI-Mode is active if V(VZAP) = V()ZAP
or Bit ENSSI is 0. The extended SSI-Mode must be