IC-MSA Datasheet, PDF (18/29 Pages) IC-Haus GmbH – SIN/COS SIGNAL CONDITIONER with AGC and 1Vpp DRIVER

iC-MSA SIN/COS SIGNAL
preliminary
CONDITIONER with AGC and 1Vpp DRIVER
INPUT CONFIGURATIONS
Rev A1, Page 18/29
All input stages are configured as instrumentation am-
plifiers and thus directly suitable for differential input
signals. Referenced input signals can be processed
as an option; in this mode input X2 acts as a reference.
Both current and voltage signals can be processed as
input signals, selected using RIN12(0) and RIN0(0).
INMODE
Code
0
1
Note
Addr 0x43, bit 2
Function
Differential input signals
Single-ended input signals *
* Input X2 is reference for all inputs.
Table 16: Input Signal Mode
Figure 2: Signal conditioning input circuit.
Current Signals
In I Mode an input resistor Rin() becomes active at
each input pin, converting the current signal into a volt-
age signal. Input resistance Rin() consists of a pad
wiring resistor and resistor Rui() which is linked to the
adjustable bias voltage source VREFin(). The follow-
ing table shows the possible selections, with Rin() giv-
ing the typical resulting input resistance (see Electrical
Characteristics for tolerances).
NB. The input circuit is not suitable for back-to-back
photodiodes.
Voltage Signals
In V Mode an optional voltage divider can be selected
which reduces unacceptably large input amplitudes to
ca. 25%. The circuitry is equivalent to the resistor
chain in I Mode; the pad wiring resistor is considerably
larger here, however.
For sensors whose offset calibration is to be propor-
tional to an external DC voltage source the reference
source can be selected using BIASEX; for all other
sensors BIASEX should be set to ’00’.
RIN12
RIN0
Code
–000
–010
–100
–110
1—1
0—1
Notes
Addr 0x4E, bit 3:0
Addr 0x53, bit 3:0
Nominal Rin() Intern Rui() I/V Mode
1.7 kΩ
1.6 kΩ
current input
2.5 kΩ
2.3 kΩ
current input
3.5 kΩ
3.2 kΩ
current input
4.9 kΩ
4.6 kΩ
current input
20 kΩ
5 kΩ
voltage input 4:1*
high
impedance
1 MΩ
voltage input 1:1
For single-ended signals identical settings of RIN0
and RIN12 are required.
*) VREFin is the voltage divider’s footpoint; input
currents may be positive or negative (Vin > VREFin,
or Vin < VREFin).
Table 17: I/V Mode and Input Resistance
BIAS12
BIAS0
Code
0
1
Addr 0x4E, bit 6
Addr 0x53, bit 6
Function
VREFin = 2.5 V
for low-side current sinks (e.g. photodiodes with
common anode at GNDS)
VREFin = 1.5 V
for high-side currrent-sources (e.g. photodiodes
with common cathode at VDDS)
for voltage sources versus ground
(e.g. iC-SM2, Wheatstone sensor bridges)
for voltage sources with low-side reference
(e.g. iC-LSHB, when using BIASEX = 11)
Table 18: Reference Voltage
BIASEX
Code
00
10
11
Notes
Addr 0x4D, bit 7:6
VREFin
Pin function of X2
internal
Input Index- (negative zero signal)
internal
Output of VREFin12*
external
Input for external reference**:
V(X2) replaces VREFin
*) Do not load, buffering recommended
**) See Elec. Char. Nos. 205 and 206
Table 19: Input Reference Selection