IC-MSA Datasheet, PDF (14/29 Pages) IC-Haus GmbH – SIN/COS SIGNAL CONDITIONER with AGC and 1Vpp DRIVER

iC-MSA SIN/COS SIGNAL
preliminary
CONDITIONER with AGC and 1Vpp DRIVER
I²C Slave Mode (ENSL = 1)
In this mode iC-MSA behaves like an I²C slave with the
device ID 0x57 and the configuration interface permits
write and read accesses to iC-MSA’s internal registers.
For chip release verification purposes an identification
value is stored under ROM address 0x5F; a write ac-
cess to this address is not permitted.
CHPREL
Code
0x10
Adr 0x5F, bit 7:0 (ROM)
Chip Release
iC-MSA
Table 7: Chip Release
NTRI
Code
0
1
Notes
Adr 0x42, bit 7
Function
Output drivers disabled
Setting the operating mode, output drivers active
NTRI is evaluated only during I²C slave mode.
Table 8: Tristate Function And Op. Mode Change
Rev A1, Page 14/29
Register
Address
0x00-0x03
0x04-0x3F
0x40-0x58
0x59
0x5A
0x5B-0x5E
0x5F
0x60-0x63
0x64-0x77
0x78
0x79-0x7A
0x7B-0x7E
0x7F
Read access in I²C slave mode (ENSL = 1)
Content
Current error memory
Not available
Configuration: register addresses 0x40-0x58
AGCGF1(10:3)
Not available
OEM data: register addresses 0x5B-0x5E
Chip release (ROM)
Configuration: register addresses 0x60-0x63
Not available
Configuration: register address 0x58
Not available
OEM data: register addresses 0x5B-0x5E
Chip release (ROM)
Table 9: RAM Read Access
Register
Address
0x40
0x41
0x42
0x43-0x56
0x57
0x58
0x59-0x5A
0x5B-0x5E
others
Write access in I²C slave mode (ENSL = 1)
Access and conditions
Changes possible, no restrictions
Changes possible (wrong entries for CFGIBN can
limit functions)
Bit 7 = 0 (NTRI): changes to bits (6:0) permitted
A change of operating mode follows only on writing
Bit 7 = 1 (NTRI); when doing so changes to bits
(6:0) are not permitted.
Changes possible, no restrictions
Bit 3 = 1 (ENSL):
changes to bits (7:4) and (2:0) permitted
Changes possible, no restrictions
Not available
Changes possible, no restrictions
No changes permitted
Table 10: RAM Write Access