IC-PV Datasheet, PDF (17/28 Pages) IC-Haus GmbH – BATTERY-BUFFERED HALL MULTITURN ENCODER

iC-PV
BATTERY-BUFFERED HALL MULTITURN ENCODER
Rev E2, Page 17/28
I2C MULTI-MASTER INTERFACE TO EEPROM INTERFACE AND CRC PROTECTION
Pins SCL and SDA form an interface which can be used
to communicate (read-only) with an external EEPROM
according to I²C protocol (with at least 128 bytes, e.g.
24C01, 24C02, 24C08 and maximum 24C16, extended
address range is not supported).
The expected slave address is 0x50 or "101 0000", the
standard I²C slave EEPROM address.
Example of CRC Calculation Routine
This EEPROM is used to store the iC-PV configuration
(addresses 0x00 to 0x0A) according to the register map
on Page 10. The configuration is protected against bit
errors by an 8 bit polynomial cyclic redundancy check.
CRC checksum failure is displayed via output NERR
and as an error bit at the end of the SSI communica-
tion protocol. The multiturn counter preload value is
stored in its own configuration area (0x05 - 0x09) and
is also saved with its own CRC on 0x0A. The CRC for
the remaining four configuration bytes (0x00 - 0x03)
is stored at address 0x04. Both CRC checksums are
generated with the polynomial X⁸ + X⁵ + X³ + X² + X¹ + 1
(0x2F sometimes also named as 0x12F). The CRC start
value is zero.
Since iC-PV does only read configuration data, the write
access to EEPROM is done via external inline program-
ming via pins SCL and SDA (I²C protocol). The direct
EEPROM access to I²C lines is shown in the applica-
tion schematic on Page 24. In applications with shared
EEPROM, e.g. with iC-MHM, the EEPROM program-
ming for iC-PV configuration can be done via the BiSS
interface of the iC-MHM (see Figure 12).
If no EEPROM is available or desired in the applica-
tion, programming the iC-PV with a microcontroller unit
(MCU) is possible. Therefore, the MCU has to emulate
an I²C slave, since iC-PV is acting as a bus master
only. At startup, after a short high pulse at pin PRE, the
iC-PV request the address 0x00 to 0x0A from the con-
nected I²C slave. This is done in a combined write/read
command as shown in Figure 11. The shown sequence
is repeated 11 times.
main() {
unsigned char Reg[11] = {0x00, 0x17, 0x03, 0x60
0x4B, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xDF};
int iCRCPoly = 0x12F;
// CRC Polynomial 100101111
unsigned char ucDataStream = 0;
unsigned char ucCRC;
// Calculate Config CRC //
ucCRC = 0;
// Startvalue !!!
for (int iReg = 0 ; iReg<4; iReg ++) {
ucDataStream = Reg[iReg];
for (int i =0; i <=7; i ++) {
if ( (ucCRC & 0x80) != (ucDataStream & 0x80
))
ucCRC = (ucCRC << 1 ) ^ iCRCPoly ;
else
ucCRC = (ucCRC << 1 ) ;
ucDataStream = ucDataStream << 1 ;
}
}
Reg[4] = ucCRC;
printf(Reg[4]);
// Calculate Counter CRC //
ucCRC = 0;
// Startvalue !!!
for (int iReg = 5 ; iReg<10; iReg ++) {
ucDataStream = Reg[iReg];
for (int i =0; i <=7; i ++) {
if ( (ucCRC & 0x80) != (ucDataStream & 0x80
))
ucCRC = (ucCRC << 1 ) ^ iCRCPoly ;
else
ucCRC = (ucCRC << 1 ) ;
ucDataStream = ucDataStream << 1 ;
}
}
Reg[10] = ucCRC;
printf(Reg[10]);
}
f
scl
SCL
SDA
S 1 0 1 0 A2 A1 A0 W ACK D7 ... D0 ACK Sr
S 1 0 1 0 A2 A1 A0 R ACK D7 … D0 ACK P
Start
cond.
Claiming
the bus
Slave Address (7 bit “1010000“)
Write ACK
(Slave)
Data (8 bit)
EEPROM
address
to read
Master requesting the address to read
(write command master to slave)
ACK Start
(Slave) repeated
condition
Keeping
the bus
Slave Address (7 bit “1010000“)
Read ACK
(Slave)
Data (8 bit)
read from
requested
address
Master reading the data at requested address
(read command master to slave)
NACK Stop
(Master) cond.
Releasing
the bus
Figure 11: iC-PV combined write/read command reading one slave address.