IC-PV Datasheet, PDF (10/28 Pages) IC-Haus GmbH – BATTERY-BUFFERED HALL MULTITURN ENCODER

iC-PV
BATTERY-BUFFERED HALL MULTITURN ENCODER
CONFIGURATION PARAMETERS
Rev E2, Page 10/28
Hall Sensor Conditioning
DIR:
Code Direction (P. 12)
OS:
Angle Offset (P. 12)
Serial Interface
INT_MODE: Serial Interface Operating Mode (P. 14)
ST_GRAY: Singleturn Input Data Format (P. 14)
MT_GRAY: Multiturn Output Data Format (P. 14)
MT_BW: Multiturn Bit Width (P. 14)
SYNC_BW: Synchronization Bit Width (P. 14)
ST_BW: Singleturn Input Bit Width (P. 15)
EN_ERR: Error Bit Enable (P. 15)
EN_PAR: Parity Bit Enable (P. 15)
Multiturn Counter
MT_PREL: Multiturn Preload Value (P. 16)
EEPROM CRC
CRC_CFG: Checksum for Chip Configuration
(0x00-0x03) (P. 17)
CRC_CTR: Checksum for MT Counter Preload
(0x05-0x09) (P. 17)
Supply Switch and Battery Monitoring
EN_BAT_MON:
Battery Monitoring Enable (P. 18)
Bias and Oscillator Calibration
IBIAS:
Bias Current Calibration (P. 18)
A_MAX: Maximum Angular Acceleration (P. 19)
REGISTER MAP (iC-PV and EEPROM)
OVERVIEW
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Interface and Hall Signal Processing
0x00
EN_PAR
EN_ERR
DIR
0x01
OS
0x02
0
0
ST_BW
Oscillator Configuration
0x03
0
EN_BAT_MON
A_MAX
CRC Configuration
0x04
CRC_CFG(7:0)
Counter Preload
0x05
MT_PREL(7:0)
0x06
MT_PREL(15:8)
0x07
MT_PREL(23:16)
0x08
MT_PREL(31:24)
0x09
MT_PREL(39:32)
CRC Counter
0x0A
CRC_CTR(7:0)
Note: Reserved registers must be programmed to zero.
Bit 2
Bit 1
Bit 0
ST_GRAY
MT_BW
MT_GRAY INT_MODE
SYNC_BW
IBIAS
Table 5: Register layout