IC-MSB_17 Datasheet, PDF (15/32 Pages) IC-Haus GmbH – SIN/COS SIGNAL CONDITIONER

iC-MSB^SAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
SERIAL CONFIGURATION INTERFACE (EEPROM)
Rev F3, Page 15/32
The serial configuration interface consists of the two
pins SCL and SDA and enables read and write access
to an EEPROM with I²C interface. The readout speed
can be adjusted using register bit ENFAST.
ENFAST
Code
0
1
Notes
Adr 0x00, bit 7
Function
Regular clock rate, f(SCL) approx. 80 kHz
High clock rate, f(SCL) approx. 320 kHz
For in-circuit programming bus lines SCL and SDA
require pull-up resistors.
For line capacitances to 170 pF, adequate values
are:
4.7 kΩ with clock frequency 80 kHz
2 kΩ with clock frequency 320 kHz
The pull-up resistors may not be less than 1.5 kΩ. To
separate the signals a ground line between SCL and
SDA is recommended.
iC-MSB requires a supply voltage during EEPROM
programming (5 V to VDD).
Example of CRC Calculation Routine
unsigned char ucDataStream = 0;
i n t iCRCPoly = 0x11D ;
unsigned char ucCRC=0;
int i = 0;
ucCRC = 1 ; / / s t a r t v a l u e ! ! !
for ( iReg = 0; iReg <31; iReg ++)
{
ucDataStream = ucGetValue ( iReg ) ;
for ( i =0; i <=7; i ++) {
i f ( ( ucCRC & 0x80 ) ! = ( ucDataStream & 0x80 ) )
ucCRC = (ucCRC << 1 ) ^ iCRCPoly ;
else
ucCRC = (ucCRC << 1 ) ;
ucDataStream = ucDataStream << 1 ;
}
}
EEPROM Selection
The following minimal requirements must be fulfilled:
Table 5: Config. Interface Clock Frequency
• Operation from 3.3 to 5 V, I²C interface
Once the supply has been switched on (power down
reset) the iC-MSB outputs are high impedance (tristate)
until a valid configuration is read out from the EEPROM
using device ID 0x50.
Bit errors in the 0x00 to 0x1E memory section are pin-
pointed by the CRC deposited in register CHKSUM(7:0)
(address 0x1F; the CRC polynomial used is "1 0001
1101").
Should no valid configuration data being available (in-
correct CRC value or EEPROM missing), the readin pro-
cess is repeated; the system aborts following a fourth
faulty attempt and iC-MSB switches to I²C slave mode.
For devices loading valid configuration data from the
EEPROM, the register bit ENSL decides for enabling
the I²C slave function.
ENSL
Code
0
1
Adr 0x17, bit 3
Function
Normal operation
I²C Slave Mode Enable (Device ID 0x55)
• Minimal 512 bit, 64x8
(address range used is 0x00 to 0x3F)
• Support of Page Write with Pages of at least 4
bytes. Otherwise error events can not be saved
to the EEPROM (EMASKE(9:0) = 0x000).
• Device ID 0x50 (’1010 000’ w/o R/W bit),
0xA0 (’1010 0000’ with R/W = 0)
• No occupation of 0x55 (A2...A0 = 0 is essential).
Otherwise iC-MSB is not accessible in I²C slave
mode via 0x55 (ENSL = 0).
Recommended devices: Atmel AT24C01, ST M24C01,
ST M24C02 (2K), ROHM BR24L01A-W, BR24L02-W
Note: When programming the EEPROM in-circuit,
note that iC-MSB must be powered up in advance to
avoid interferences by its I²C master.
Table 6: Config. Interface Mode
The device ID for the EEPROM can be entered in regis-
ter DEVID(6:0) (address 0x00), from which iC-MSB will
take its configuration after exiting test mode (see page
19). The DEVID(6:0) stored therein is then accepted.