HYMP112P72CP8-C4 Datasheet, PDF (9/32 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs

1240pin Registered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(512Mbx72): HYMP151P72CP8
RDOT0
RCKE0
RS0
DQS0
DQS0
DQ7-0
DM0
DQS
DQS
DQ7-0
DM
D0
RS1
DQS
DQS
DQ7-0 _D9
DM
RDOT1
RCKE1
RS2
DQS
DQS
DQ7-0
DM
D18
RS3
DQS
DQS
DQ7-0
DM
D27
Serial PD
SCL
SDA
WP A0 A1 A2
SA0 SA1 SA2
DQS1
DQS1
DQ15-8
DM1
DQS2
DQS2
DQ23-16
DM2
DQS
DQS
DQ7-0
DM
D1
DQS
DQS
DQ7-0
DM
D2
DQS
DQS
DQ7-0
DM
D10
DQS
DQS
DQ7-0
DM
D11
DQS
DQS
DQ7-0
DM
D19
DQS
DQS
DQ7-0
DM
D20
DQS
DQS
DQ7-0
DM
D28
DQS
DQS
DQ7-0
DM
D29
VDDSPD
VDD/VDDQ
VREF
VSS
SPD
D0–D35
D0–D35
D0–D35
DQS3
DQS3
DQ31-24
DM3
DQS4
DQS4
CB7-0
DM8
DQS
DQS
DQ7-0
DM
D3
DQS
DQS
DQ7-0
DM
D4
DQS
DQS
DQ7-0
DM
D12
DQS
DQS
DQ7-0
DM
D13
DQS
DQS
DQ7-0
DM
D21
DQS
DQS
DQ7-0
DM
D22
DQS
DQS
DQ7-0
DM
D30
DQS
DQS
DQ7-0
DM
D31
CK0
P
CK0 L
L
RESET ^OE
PCK0-PCK6, PCK8,PCK9
-> CK: SDRAMs D0-D35
PCK0-PCK6, PCK8, PCK9
-> CK: SDRAMs D0-D35
PCK7 -> CK: Register
PCK7 -> CK: Register
DQS4
DQS4
DQ39-32
DM4
DQS5
DQS5
DQ47-40
DM5
DQS6
DQS6
DQ55-48
DM6
DQS7
DQS7
DQ63-56
DM7
DQS
DQS
DQ7-0
DM
D5
DQS
DQS
DQ7-0
DM
D6
DQS
DQS
DQ7-0
DM
D7
DQS
DQS
DQ7-0
DM
D8
DQS
DQS
DQ7-0
DM
D14
DQS
DQS
DQ7-0
DM
D15
DQS
DQS
DQ7-0
DM
D16
DQS
DQS
DQ7-0
DM
D17
DQS
DQS
DQ7-0
DM
D23
DQS
DQS
DQ7-0
DM
D24
DQS
DQS
DQ7-0
DM
D25
DQS
DQS
DQ7-0
DM
D26
DQS
DQS
DQ7-0
DM
D32
DQS
DQS
DQ7-0
DM
D33
DQS
DQS
DQ7-0
DM
D34
DQS
DQS
DQ7-0
DM
D35
Signals for Address and Command
Parity Function
Register A1
Vss
C0
VDD
C1
PAR_IN
PPO
QERR
Register B1
V_DD
C0
VDD
C1
PAR_IN
PPO
QERR
Register A2
Vss
C0
VDD
C1
PAR_IN
PPO
QERR
Err_Out
S0,S2*
S1,S3*
1:2
BA0-BA2***
R
A0-A15***
E
RAS
G
CAS
I
WE
S
CKE0
T
CKE1
E
ODT0
R
ODT1
RESET**
RST
PCK7**
PCK7**
RS0 -> CS: SDRAMs D0-D8, RS2 -> CS: SDRAMs D18-D26
RS1 -> CS: SDRAMs D9-D17,RS3 -> CS: SDRAMs D27-D35
RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D35****
RA0-RA15 -> A0-A15: SDRAMs D0-D35****
RRAS -> RAS: SDRAMs D0-D35
RCAS -> CAS: SDRAMs D0-D35
RWE -> WE: SDRAMs D0-D35
RCKE0 -> CKE: SDRAMs D0-D17
RCKE1 -> CKE: SDRAMs D18-D35
RODT0 -> ODT0: SDRAMs D0-D8
RODT1 -> ODT1: SDRAMs D18-D26
Register B2
V_DD
C0
VDD
C1
PAR_IN
PPO
QERR
Register A1 and A2 share the a part of
Addr/Cmd input signal set.
Register B1 and B2 chare the rest part of
Addr/Cmd input signal set.
The resistors on Par_In, A13, A14. A15,BA2 and
the signal line of Err_Out refer to the section:
The register Options for Unused Address inputs?
* S0 (S2) connects to DCS0, S1 (S3) to DCS1 on a Register A. S1 (S3) connects to DCS and S0 (S2) connects to CSR on another pair of Register.
* S2 and S3 have required pull up resistors (100k ohms), not indicated here.
** RESET, PCK7 and PCK7 connect to all Registers. Other signals connect to two of four Registers.
*** A13-15, BA2 have the optional pull down resistors(100K ohms), which is not indicated here.
**** For Raw Card N2, DQ stub resistor value is TBD.
And for Raw Card N2, post register A14 and A15 are not connected to the SDRAMs.
Rev. 0.7 / Jun. 2009
9