HYMP112P72CP8-C4 Datasheet, PDF (1/32 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs

240pin Registered DDR2 SDRAM DIMMs based on 1Gb version C
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version C DDR2
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb
version C based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width
form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
• JEDEC standard Double Data Rate2 Synchro-
nous DRAMs (DDR2 SDRAMs) with 1.8V +/-
0.1V Power Supply
• All inputs and outputs are compatible with
SSTL_1.8 interface
• 8 Bank architecture
• Posted CAS
• Programmable CAS Latency 3, 4, 5, 6
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both
sequential and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60 ball(x4/x8)
• 133.35 x 30.00 mm form factor
• RoHS compliant
ORDERING INFORMATION
Part Name
Density
HYMP112P72CP8-C4/Y5/S6/S5
1GB
HYMP125P72CP8-C4/Y5/S6/S5
2GB
HYMP125P72CP4-C4/Y5/S6/S5
2GB
HYMP151P72CP8-C4/Y5/S6/S5
4GB
HYMP151P72CP4-C4/Y5/S6/S5
4GB
HYMP31GP72CMP4-C4/Y5
8GB
HYMP112R72CP8-E3/C4
1GB
HYMP125R72CP4-E3/C4
2GB
HYMP151R72CP4-E3/C4
4GB
Organization
128Mx72
256Mx72
256Mx72
512Mx72
512Mx72
512Mx72
128Mx72
256Mx72
512Mx72
# of
DRAMs
9
18
18
36
36
72
9
18
36
# of
ranks
1
2
1
4
2
4
1
1
2
Parity
Support
O
O
O
O
O
O
X
X
X
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.7 / Jun. 2009
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