HYMP112P72CP8-C4 Datasheet, PDF (22/32 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs

1240pin Registered DDR2 SDRAM DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin (CL-tRCD-tRP)
Parameter
CAS Latency
tRCD
tRP
tRC
tRAS
DDR2-800 (S5)
5-5-5
min
5
12.5
12.5
57.5
45
DDR2-667 (Y5)
5-5-5
min
5
15
15
60
45
DDR2-533 (C4)
4-4-4
min
4
15
15
60
45
DDR2-400 (E3)
3-3-3
min
3
15
15
55
40
Unit
ns
ns
ns
ns
ns
AC Timing Parameters by Speed Grade (DDR2-400 & DDR2-533)
Parameter
Symbol
DDR2-400
Min
Max
Data-Out edge to Clock edge Skew
tAC
-600
600
DQS-Out edge to Clock edge Skew
tDQSCK
-500
500
Clock High Level Width
tCH
0.45
0.55
Clock Low Level Width
tCL
0.45
0.55
Clock Half Period
tHP
min
(tCL, tCH)
-
System Clock Cycle Time
tCK
5000
8000
DQ and DM input setup time
tDS
150
-
DQ and DM input hold time
tDH
275
-
Control & Address input Pulse Width for each input
tIPW
0.6
-
DQ and DM input pulse width for each input pulse width for
each input
tDIPW
0.35
-
Data-out high-impedance window from CK, /CK
tHZ
-
tAC max
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write preamble
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPRE
tAC min
2*tAC min
-
-
tHP - tQHS
WL - 0.25
0.35
0.35
0.2
0.2
2
0.35
tAC max
tAC max
350
450
-
WL + 0.25
-
-
-
-
-
-
DDR2-533
Min
Max
-500
500
-500
450
0.45
0.55
0.45
0.55
min
(tCL, tCH)
-
3750
8000
100
-
225
-
0.6
-
Unit Note
ps
ns
CK
CK
ns
ps
ps
1
ps
1
tCK
0.35
-
tCK
-
tAC min
2*tAC min
-
-
tHP - tQHS
WL - 0.25
0.35
0.35
0.2
0.2
2
0.35
tAC max ps
tAC max ps
tAC max ps
300
ps
400
ps
-
ps
WL + 0.25 tCK
-
tCK
-
tCK
-
tCK
-
tCK
-
tCK
-
tCK
Rev. 0.7 / Jun. 2009
23