 English |
|
|
|
|
|
|
|
| HYMP112P72CP8-C4 Datasheet, PDF (13/32 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs | |||
| |||
| ◁ |
INPUT DC LOGIC LEVEL
1240pin Registered DDR2 SDRAM DIMMs
Parameter
Symbol
dc Input logic HIGH
dc Input logic LOW
VIH(DC)
VIL(DC)
INPUT AC LOGIC LEVEL
Min
VREF + 0.125
-0.30
Max
VDDQ + 0.3
VREF - 0.125
Unit
Note
V
V
Parameter
Symbol
ac Input logic HIGH VIH(AC)
ac Input logic LOW VIL(AC)
DDR2 400/533
Min
Max
VREF + 0.250
-
-
VREF - 0.250
DDR2 667/800
Min
Max
VREF + 0.200
-
-
VREF - 0.200
Unit
V
V
Notes
AC INPUT TEST CONDITIONS
Symbol
VREF
VSWING(MAX)
SLEW
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
Value
0.5 * VDDQ
1.0
1.0
Units
V
V
V/ns
Notes
1
1
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF max to VIH(ac) min for rising edges and the
range from VREF min to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions and VIH (ac) to
VIL (ac) on the negative transitions.
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
VSWING(MAX)
âTF
âTR
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
Falling Slew =
VREF - VIL(ac) max
âTF
Rising Slew =
VIH(ac) min - VREF
âTR
< Figure: AC Input Test Signal Waveform >
Rev. 0.7 / Jun. 2009
13
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese