HYMP112P72CP8-C4 Datasheet, PDF (4/32 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs

1240pin Registered DDR2 SDRAM DIMMs
PIN DESCRIPTION
Pin
Pin Description
CK0
Clock Input, positive line
CK0
Clock input, negative line
CKE0~CKE1 Clock Enable Input
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
S0,S1
Chip Select Input
A0~A9,A11~A13 Address input
A10/AP
Address input/Autoprecharge
BA0, BA1, BA2 SDRAM Bank Address
SCL
Serial Presence Detect (SPD) Clock Input
SDA
SA0~SA2
Par_In
Err_Out
RESET
CB0~CB7
SPD Data Input/Output
E²PROM Address Inputs
Parity bit for the Address and Control bus
Parity error found on the Addre
Reset Enable
Data Strobe Inputs/Outputs
Pin
Pin Description
ODT[1:0]
On Die Termination Inputs
VDDQ
DQs Power Supply
DQ0~DQ63
Data Input/Output
CB0~CB7
Data check bits Input/Output
DQS(0~8)
Data strobes
DQS(0~8)
Data strobes, negative line
DM(0~8),DQS(9~17) Data Maskes/Data strobes
DQS(9~17)
Data strobes, negative line
RFU
Reserved for Future Use
NC
No Connect
TEST
Memory bus test tool (Not Connected and Not
Usable on DIMMs)
VDD
Core Power
VDDQ
I/O Power Supply
VSS
Ground
VREF
Reference Power Supply
VDDSPD
Power Supply for SPD
PIN LOCATION
pin #1
Front Side
Pin #64 Pin #65
Pin #120
Pin #121
Back Side ^{Pin #184 Pin #185}
pin #240
Rev. 0.7 / Jun. 2009
4