HY5V52F Datasheet, PDF (9/13 Pages) Hynix Semiconductor – 4Banks x 2M x 32bits Synchronous DRAM

Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
DC CHARACTERISTICS II (TA= 0 to 70^oC)
Parameter
Symbol
Test Condition
Speed
H
P
S
Operating Current
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
120
110
Precharge Standby Current ^{IDD2P CKE ≤ VIL(max), tCK = 15ns}
2
in Power Down Mode
IDD2PS CKE ≤ VIL(max), tCK = ∞
1
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
IDD2N
Precharge Standby Current
Input signals are changed one time during
2clks.
15
in Non Power Down Mode
All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
15
Active Standby Current
IDD3P CKE ≤ VIL(max), tCK = 15ns
5
in Power Down Mode
IDD3PS CKE ≤ VIL(max), tCK = ∞
5
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Active Standby Current
IDD3N
Input signals are changed one time during
2clks.
30
in Non Power Down Mode
All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
20
Burst Mode Operating Cur-
rent
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
CL=3
150
130
CL=2
160
140
Uni Not
te
mA 1
mA
mA
mA
mA
mA
mA 1
Auto Refresh Current
IDD5 tRC ≥ tRC(min), All banks active
220
mA 2
Self Refresh Current
IDD6 CKE ≤ 0.2V
Normal
Low Power
3
mA 3
1.5
Note :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. HY5V52F(P) Series : Normal, HY5V52LF(P) Series : Low Power
Rev. 0.1 / June. 2004
9