HY5V52F Datasheet, PDF (8/13 Pages) Hynix Semiconductor – 4Banks x 2M x 32bits Synchronous DRAM

Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
CAPACITANCE (TA= 0 to 70 ^oC, f=1MHz, VDD=3.3V)
Parameter
Input capacitance
Data input / output capaci-
tance
Pin
CLK
A0 ~ A12, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM0~3
DQ0 ~ DQ31
Symbol
CI1
CI2
Min Max Unit
2.0
4.0
pF
2.0
4.0
pF
CI/O
3.5
6.5
pF
Note 1.
Output
Vtt=1.4V
RT=500 Ω
30pF
Output
Z0 = 50Ω
Vtt=1.4V
RT=50 Ω
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERRISTICS I (TA= 0 to 70^oC)
Parameter
Symbol
Min
Input Leakage Current
ILI
-1
Output Leakage Current
ILO
-1
Output High Voltage
VOH
2.4
Output Low Voltage
VOL
-
Note :
1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 3.6
Max
1
1
-
0.4
Unit
uA
uA
V
V
Note
1
2
IOH = -2mA
IOL = +2mA
Rev. 0.1 / June. 2004
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