HY5V52F Datasheet, PDF (4/13 Pages) Hynix Semiconductor – 4Banks x 2M x 32bits Synchronous DRAM

Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
Ball FUNCTION DESCRIPTIONS
SYMBOL
Ball NAME
TYPE
DESCRIPTION
CLK
Clock
INPUT
The system clock input. All other inputs are registered to the SDRAM on
the rising edge of CLK.
CKE
Clock Enable
INPUT
Controls internal clock signal and when deactivated, the SDRAM will be
one of the states among power down, suspend or self refresh
CS
Chip Select
INPUT Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1 Bank Address
INPUT
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11 Address
INPUT
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS,
WE
Row Address
Strobe,
Column Address
Strobe, Write
Enable
INPUT
RAS, CAS and WE define the operation
Refer function truth table for details
DQM0~3
Data Input/Output
Mask
I/O
Controls output buffers in read mode and masks input data in write
mode
DQ0 ~
DQ31
Data Input/Output SUPPLY Multiplexed data input / output pin
NC
No Connection
-
No Connection
Rev. 0.1 / June. 2004
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