HY5V52F Datasheet, PDF (11/13 Pages) Hynix Semiconductor – 4Banks x 2M x 32bits Synchronous DRAM

Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
RAS Cycle Time
Operation
RAS Cycle Time
Auto Refresh
RAS to CAS Delay
RAS Active Time
RAS Precharge Time
RAS to RAS Bank Active Delay
CAS to CAS Delay
Write Command to Data-In Delay
Data-in to Precharge Command
Data-In to Active Command
DQM to Data-Out Hi-Z
DQM to Data-In Mask
MRS to New Command
Precharge to Data Output
High-Z
CAS Latency=3
CAS Latency=2
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
H
P
S
Symbol
Unit Note
Min Max Min Max Min Max
tRC
65 - 70 - 70 - ns
tRRC
65 - 70 - 70 - ns
tRCD
20 - 20 - 20 - ns
tRAS
45 100K 50 100K 50 100K ns
tRP
20 - 20 - 20 - ns
tRRD
15 - 20 - 20 - ns
tCCD
1 - 1 - 1 - CLK
tWTL
0 - 0 - 0 - CLK
tDPL
2 - 2 - 2 - CLK
tDAL
tDQZ
tDPL + tRP
2 - 2 - 2 - CLK
tDQM
0 - 0 - 0 - CLK
tMRD
2 - 2 - 2 - CLK
tPROZ3
3 - 3 - 3 - CLK
tPROZ2
2 - 2 - 2 - CLK
tDPE
1 - 1 - 1 - CLK
tSRE
1 - 1 - 1 - CLK 1
tREF
- 64 - 64 - 64 ms
Note :
1. A new command can be given tRC after self refresh exit.
Rev. 0.1 / June. 2004
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