HY5V52F Datasheet, PDF (5/13 Pages) Hynix Semiconductor – 4Banks x 2M x 32bits Synchronous DRAM

Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 32 I/O Synchronous DRAM
CLK
CKE
CS
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
Self refresh
logic & timer
Internal Row
Counter
Row Active
Row
Pre
Decoder
Refresh
Column Active
Column
Pre
Decoder
2Mx32 BANK 3
2Mx32 BANK 2
2Mx32 BANK 1
2Mx32 BANK 0
Memory
Cell
Array
Y-Decoder
DQ0
DQ31
Bank Select
Column Add
Counter
A0
Address
A1
Register
Burst
Counter
Pipe Line
A11
Mode Register
CAS Latency
Data Out Control
Control
BA1
BA0
Rev. 0.1 / June. 2004
5