HY5V52F Datasheet, PDF (2/13 Pages) Hynix Semiconductor – 4Banks x 2M x 32bits Synchronous DRAM

Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
DESCRIPTION
The Hynix HY5V52(L)F(P) series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applica-
tions which require wide data I/O and high bandwidth. HY5V52(L)F(P) is organized as 4banks of 2,097,152x32.
HY5V52(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
• Voltage : VDD, VDDQ 3.3V
• Auto refresh and self refresh
• All device pins are compatible with LVTTL interface • 4096 Refresh cycles / 64ms
• 90Ball FBGA with 0.8mm of pin pitch
• Programmable Burst Length and Burst Type
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by DQM0,1,2 and 3
• Internal four banks operation
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
• Burst Read Single Write operation
ORDERING INFORMATION
Part No.
HY5V52(L)F-H
HY5V52(L)F-P
HY5V52(L)F-S
HY5V52(L)FP-H
HY5V52(L)FP-P
HY5V52(L)FP-S
Clock
Frequency
133MHz
100MHz
100MHz
133MHz
100MHz
100MHz
Note
1. HY5V52F Series : Normal power
2. HY5V52LF Series : Low Power
3. HY5V52xF Series : Leaded 90Ball FBGA
4. HY5V52xFP Series : Lead Free 90Ball FBGA
CAS
Latency
3
2
3
3
2
3
Organization
Interface
4Banks x 2Mbits
x32
LVTTL
90 Ball FBGA
Leaded
Lead Free
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1 / June. 2004
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