HY51VS17403HG Datasheet, PDF (9/11 Pages) Hynix Semiconductor – 4M x 4Bit EDO DRAM

HY51V(S)17403HG/HGL
Notes :
1. AC measurements assume tT = 2ns
2. AC initial pause of 200us is required after power up followed by a minimum of eight initialization cycles
( any combination of cycles containing /RAS-only refresh or /CAS-before-/RAS refresh)
If the internal refresh counter is used, a minimum of eight /CAS-before-/RAS refresh cycle are required.
3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only : if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only : if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
5. Either tODD or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals, also transition times
are measured between VIH(min) and VIL(max)
8. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown
9. Measured with a load circuit equivalent to 1 TTL loads and 100pF.( VOH=2.0V, VOL=0.8V)
10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max)
11. Assumes that tRAD>=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max)
12. Either tRCH of tRRH must be satified for a read cycles
13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only : If tWCS >=tWCS(min), the cycle is an early write
cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle :
If tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell : if neither of the above sets of conditions
is satified, the condition of the data out (at access time) is indeterminate.
15. These parameters are referenced to /CAS leading edge in early write cycles and to /WE
leading edge in delayed write or read-modify-write cycles
16. tRASP defines /RAS pulse width in EDO page mode cycles
Rev.0.1/Apr.01
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