HY51VS17403HG Datasheet, PDF (10/11 Pages) Hynix Semiconductor – 4M x 4Bit EDO DRAM

HY51V(S)17403HG/HGL
17. Access time is determined by the longest among tAA or tCAC or tACP
18. The 16M DRAM offers 16 bit time saving parallel test mode. Address CA0 and CA1 for the 4Mx4 are
dont’ care during test mode. Test mode is set by performing a /WE-and-/CAS-before-/RAS(WCBR)
cycle. In 16bit parallel test mode, data is written into 4 bits in parallel at each I/O(I/O 1 to I/O4) and
read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state
during test mode read cycle, then the device has passed. If they are not equal, Data output pin is a
low state, then the device has failed. Refresh during test mode operation can be performed by normal
read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode,
perform either a regular /CAS-before-/RAS refresh cycle or /RAS-only refresh cycle.
19. In a test mode read cycle, the value of tRAC, tAA, tCAC and tACP is delayed by 2ns to 5ns for the
specified value. These parameters should be specified in test mode cycles by adding the above value
to the specified value in this data sheet
20. tHPC(min) can be achieved during a series of EDO page mode write cycles or EDO page mode read
cycles. If both write and read operation are mixed in a EDO page mode /RAS cycle(EDO page mode
mix cycle (1)(2)), minimum value of /CAS cycle(tCAS+tCP+2tT) becomes greater than the specified
tHPC(min) value. The value of /CAS cycle time of mixed EDO page mode is shown in EDO page mode
mix cycle (1) and (2)
Rev.0.1/Apr.01
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