HY51VS17403HG Datasheet, PDF (5/11 Pages) Hynix Semiconductor – 4M x 4Bit EDO DRAM

HY51V(S)17403HG/HGL
CAPACITANCE (Vcc=3.3V +/-10%, TA=25°C)
Parameter
Symbol
Min.
Max
Unit
Input capacitance (Address)
CI1
-
Input capacitance (Clocks)
CI2
-
Output capacitance (Data-in, Data-out)
CI/O
-
5
pF
7
pF
7
pF
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /CAS = VIH to disable Dout
Note
1
1
1, 2
AC CHARACTERISTICS (Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 18)
Test Condition
• Input rise and fall times = 2ns
• Input levels : VIL=0V, VIH=3V
• Input timing reference level : VIL/VIH = 0.8/2.0V
• Output timing reference level :
VOL/VOH=0.8/0.2V
• Output load : 1 TTL gate + CL (100pF)
( including scope and jig )
Read, Write, Read-modify-Write and Refresh Cycle
Parameter
Random read or write cycle time
/RAS precharge time
/CAS precharge time
/RAS pulse width
/CAS pulse width
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
/RAS to /CAS delay time
/RAS to Column address delay time
/RAS hold time
/CAS hold time
/CAS to /RAS precharge time
Symbol
tRC
tRP
tCP
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
-50
Min Max
84
-
30
-
8
-
50 10,000
8 10,000
0
-
8
-
0
-
8
-
12
37
10
25
10
-
35
-
5
-
-60
Min Max
104
-
40
-
10
-
60 10,000
10 10,000
0
-
10
-
0
-
10
-
14
45
12
30
13
-
40
-
5
-
-70
Unit
Min Max
124
-
ns
50
-
ns
13
-
ns
70 10,000 ns
13 10,000 ns
0
-
ns
10
-
ns
0
-
ns
13
-
ns
14
52
ns
12
35
ns
13
-
ns
45
-
ns
5
-
ns
Note
3
4
Rev.0.1/Apr.01
5