HYMD116M725B8-J Datasheet, PDF (8/19 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM SO-DIMM

HYMD116M725B(L)8-J/M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter Symbol
Test Condition
Speed
Unit Note
-J -M -K -H -L
Operating Current
One bank; Active - Precharge; tRC=tRC(min);
IDD0
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs ^{720 720 640 640 640}
mA
changing once per clock cycle
Operating Current
One bank; Active - Read - Precharge;
IDD1
Burst Length= 2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per
880
880
800
800
640
mA
clock cycle
Precharge Power
Down Standby
Current
IDD2P
All banks idle; Power down mode ; CKE=Low,
tCK=tCK(min)
160 120 120 120 120 mA
/CS=High, All banks idle; tCK=tCK(min);
Idle Standby Current
IDD2F
CKE=High; address and control inputs changing
once per clock cycle.
320
280
280
280
280
mA
VIN=VREF for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
160
mA
/CS=HIGH; CKE=HIGH; One bank; Active-
Active Standby
Current
IDD3N
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,
DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
320
mA
once per clock cycle
Operating Current
Burst=2; Reads; Continuous burst; One bank
IDD4R active; Address and control inputs changing once 1840 1520 1520 1520 1200 mA
per clock cycle; tCK=tCK(min); IOUT = 0mA
Operating Current
Burst=2; Writes; Continuous burst; One bank
IDD4W
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS ^{1840 1520 1520 1520 1200}
mA
inputs changing twice per clock cycle
Auto Refresh
Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; 1280 1200 1200 1200 1120 mA
distributed refresh
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Normal
Low Power
16
8
mA
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4, Refer to the
following page for detailed test condition
2400 2080 2080 2080 1760 mA
Rev. 0.2/Aug. 02
8