HYMD116M725B8-J Datasheet, PDF (18/19 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM SO-DIMM

HYMD116M725B(L)8-J/M/K/H/L
SERIAL PRESENCE DETECT
Bin Sort :J(DDR333),M(DDR266(2-2-2),K(DDR266A@CL=2)
H(DDR266B@CL=2.5),L(DDR200@CL=2)
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36~40
41
42
43
44
45
46~61
62
63
64
65~71
Function Description
Function Supported
J
M
K
H
L
Hexa Value
Note
JMKH L
Number of Bytes written into serial memory at module
manufacturer
128 Bytes
80h
Total number of Bytes in SPD device
256 Bytes
08h
Fundamental memory type
DDR SDRAM
07h
Number of row address on this assembly
12
0Ch
1
Number of column address on this assembly
10
0Ah
1
Number of physical banks on DIMM
1Bank
01h
Module data width
72 Bits
48h
Module data width (continued)
-
00h
Module voltage Interface levels(VDDQ)
SSTL 2.5V
04h
DDR SDRAM cycle time at CAS Latency =2.5(tCK)
6.0ns 7.5ns 7.5ns 7.5ns 8.0ns 60h 75h 75h 75h 80h 2
DDR SDRAM access time from clock at CL=2.5 (tAC) +/-0.7ns
+/-0.75ns
+/-0.8ns 70h 75h 75h 75h 80h 2
Module configuration type
ECC
02h
Refresh rate and type
15.6us & Self refresh
80h
Primary DDR SDRAM width
x8
08h
Error checking DDR SDRAM data width
x8
08h
Minimum clock delay for back-to-back random column
address(tCCD)
1 CLK
01h
Burst lengths supported
2,4,8
0Eh
Number of banks on each DDR SDRAM
4 Banks
04h
CAS latency supported
2, 2.5
0Ch
CS latency
0
01h
WE latency
1
02h
DDR SDRAM module attributes
Differential Clock Input
20h
DDR SDRAM device attributes : General
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
C0h
tRAS Lock Out
DDR SDRAM cycle time at CL=2.0(tCK)
7.5ns 7.5ns 7.5ns 10ns 10ns 75h 75h 75h A0h A0h
DDR SDRAM access time from clock at CL=2.0(tAC) +/-0.7ns
+/-0.75ns
+/-0.8ns 70h 75h 75h 75h 80h
DDR SDRAM cycle time at CL=1.5(tCK)
-
00h
DDR SDRAM access time from clock at CL=1.5(tAC)
-
00h
Minimum row precharge time(tRP)
18ns 15ns 20ns 20ns 20ns 48h 3Ch 50h 50h 50h
Minimum row activate to row active delay(tRRD)
12ns 15ns 15ns 15ns 15ns 30h 3Ch 3Ch 3Ch 3Ch
Minimum RAS to CAS delay(tRCD)
18ns 15ns 20ns 20ns 20ns 48h 3Ch 50h 50h 50h
Minimum active to precharge time(tRAS)
42ns 45ns 45ns 45ns 50ns 2Ah 2Dh 2Dh 2Dh 32h
Module row density
128MB
20h
Command and address signal input setup time(tIS) 0.75ns 0.9ns 0.9ns 0.9ns 1.1ns 75h 90h 90h 90h B0h
Command and address signal input hold time(tIH)
0.75ns 0.9ns 0.9ns 0.9ns 1.1ns 75h 90h 90h 90h B0h
Data signal input setup time(tDS)
0.45ns 0.5ns 0.5ns 0.5ns 0.6ns 45h 50h 50h 50h 60h
Data signal input hold time(tDH)
0.45ns 0.5ns 0.5ns 0.5ns 0.6ns 45h 50h 50h 50h 60h
Reserved for VCSDRAM
Undefined
00h
Minimum active / auto-refresh Time (tRC)
60ns 60ns 65ns 65ns 70ns 3Ch 3Ch 41h 41h 46h
Minimum auto-refresh to active / auto-refresh com-
mand period(tRFC)
72ns 75ns 75ns 75ns 80ns 48h 4Bh 4Bh 4Bh 50h
Maximum cycle time (tCK max)
12ns 12ns 12ns 12ns 12ns 30h 30h 30h 30h 30h
Maximum DQS-DQ skew time (tDQSQ)
0.45ns 0.5ns 0.5ns 0.5ns 0.6ns 2Dh 32h 32h 32h 3Ch
Maximum read data hold skew factor (tQHS)
0.55ns 0.75ns 0.75ns 0.75ns 0.75ns 55h 75h 75h 75h 75h
Superset Information (may be used in future)
Undefined
00h
SPD Revision code
Initial release
00h
Checksum for Bytes 0~62
-
EFh 79h A6h D1h 6Bh
Manufacturer JEDEC ID Code
Hynix JEDEC ID
ADh
------ Manufacturer JEDEC ID Code
-
00h
Rev. 0.2/Aug. 02
18