HYMD116M725B8-J Datasheet, PDF (6/19 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM SO-DIMM

CAPACITANCE (TA=25^oC, f=100MHz )
HYMD116M725B(L)8-J/M/K/H/L
Parameter
Pin
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Data Input / Output Capacitance
A0 ~ A11, BA0, BA1
/RAS, /CAS, /WE
CKE0, CKE1
/CS0, /CS1
CK0, /CK0, CK1, /CK1
DM0 ~ DM7
DQ0 ~ DQ63, DQS0 ~ DQS7
Note :
1. VDD=min. to max., VDDQ=2.3V to 2.7V, VODC=VDDQ/2, VOpeak-to-peak=0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
Min
Max
Unit
pF
pF
pF
pF
pF
pF
pF
Output
VTT
RT=50Ω
Zo=50Ω
CL=30pF
VREF
Rev. 0.2/Aug. 02
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