HY67V161610D Datasheet, PDF (7/11 Pages) Hynix Semiconductor – 2 Banks x 512K x 16 Bit Synchronous DRAM

HY57V161610D
A C C H A R A C T E R IS T IC S ( T A = 0 °C t o 7 0 °C , V D D = 3 . 0 V t o 3 . 6 V , V S S = 0 V ^Note1,2 )
Parameter
System clock
cycle time
CL=3
CL=2
Clock high pulse width
Clock low pulse width
Access time
from clock
CL=3
CL=2
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in low Z-
time
CLK to data output in high Z-
time
Symbol
-5
Min
Max
tCK3
5
tCK2
-
tCHW
1.75
tCLW
1.75
tAC3
4.5
tAC2
tOH
1.5
tDS
1.5
tDH
1
tAS
1.5
tAH
1
tCKS
1.5
tCKH
1
tCS
1.5
tCH
1
-55
M in
Max
5.5
-
2
2
5
2
1.5
1
1.5
1
1.5
1
1.5
1
-6
M in
Max
6
-
10
-
2
-
2
-
-
5.5
-
6
2
-
1.5
-
1
-
1.5
-
1
-
1.5
-
1
-
1.5
-
1
-
-7
M in
7
Max
-
10
-
2.5
-
2.5
-
-
6
-
6
2.5
-
1.75
-
1
-
1.75
-
1
-
1.75
-
1
-
1.75
-
1
-
-8
M in M a x
8
-
12
-
3
-
3
-
-
6
-
6
2.5
-
2
-
1
-
2
-
1
-
2
-
1
-
2
-
1
-
-10
M in
10
Max
-
12
-
3
-
3
-
-
7
-
7
2.5
-
2.5
-
1
-
2.5
-
1
-
2.5
-
1
-
2.5
-
1
-
tOLZ
2
2
2
-
2
-
2
-
2
-
tOHZ
2
5
2
5.5
2
6
2
7
2
8
3
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
3
4
4
3
4
4
4
4
4
4
4
4
Note :
1.V DD (min) is 3.15V when HY57V161610DTC-7 operates at C A S latency=2 and tCK2=8.9ns.
2.V DD (min) of HY57V161610DTC-5/55 is 3.15V
3.tCK2 is 8.9ns only when tAC2 is 7.9ns in HY57V161610DTC-6 and HY57V161610DTC-7.
4.Assume tR / tF (input rise and fall time ) is 1ns.
Rev. 3.6/Apr.01
7