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HY67V161610D Datasheet, PDF (10/11 Pages) Hynix Semiconductor – 2 Banks x 512K x 16 Bit Synchronous DRAM | |||
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COMMAND TRUTH TABLE
HY57V161610D
Command
Mode Register Set
No Operation
Bank Active
Read
Read with Auto precharge
Write
Write with Auto precharge
Precharge All Bank
Precharge selected Bank
Burst Stop
U/LDQM
Auto Refresh
Burst-READ-Single-WRITE
Self Refresh1
Entry
Exit
Precharge power
down
Entry
Exit
Clock Suspend
Entry
Exit
CKEn-1
CKEn
CS
H
X
L
H
H
X
L
H
X
L
H
X
L
H
X
L
H
X
L
H
X
L
H
H
H
L
H
X
L
H
L
L
H
L
H
L
H
H
L
L
H
L
H
L
H
H
L
L
L
H
RAS
CAS
L
L
X
X
H
H
L
H
H
L
H
L
L
H
H
H
X
L
L
L
L
L
L
X
X
H
H
X
X
H
H
X
X
H
H
X
X
V
V
X
WE
L
X
H
H
H
L
L
L
H
L
H
X
H
X
H
X
H
X
V
DQM
X
X
X
X
X
X
X
V
X
X
X
X
X
X
X
X
A10/
A0~A 9
BA
AP
OP code
X
Row Address
V
L
Column
Address
V
H
L
Column
Address
V
H
H
X
X
L
V
X
X
X
A9 Pin High
(Other Pins OP code)
X
X
X
Note
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. X=Do not care, L=Low, H=High, BA=Bank Address, RA= Row Address, CA=Column Address, Opcode=Operand Code,
NOP=No Operation.
Rev. 3.6/Apr.01
10
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