GMS81C1102 Datasheet, PDF (65/89 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C1102 / GMS81C1202
20. WATCHDOG TIMER
The purpose of the watchdog timer is to detect the mal-
function (runaway) of program due to external noise or
other causes and return the operation to the normal condi-
tion.
The watchdog timer has two types of clock source.
The first type is an on-chip RC oscillator which does not
require any external components. This RC oscillator is sep-
arate from the external oscillator of the Xin pin. It means
that the watchdog timer will run, even if the clock on the
Xin pin of the device has been stopped, for example, by en-
tering the STOP mode.
The other type is a prescaled system clock.
The watchdog timer consists of 7-bit binary counter and
the watchdog timer data register. The source clock of
WDT is overflow of Basic Interval Timer. When the value
of 7-bit binary counter is equal to the lower 7 bits of
WDTR, the interrupt request flag is generated. This can be
used as WDT interrupt or CPU reset signal in accordance
with the bit WDTON .
Note: Because the watchdog timer counter is enabled af-
ter clearing Basic Interval Timer, after the bit WD-
TON set to "1", maximum error of timer is depend on
prescaler ratio of Basic Interval Timer.
The 7-bit binary counter is cleared by setting WDTCL(bit7
of WDTR) and the WDTCL is cleared automatically after
1 machine cycle.
The RC oscillated watchdog timer is activated by setting
the bit RCWDT of CKCTLR and executing the STOP in-
struction as shown below.
:
LDM
LDM
STOP
NOP
NOP
:
CKCTLR,#3FH ; enable the RC-osc WDT
WDTR,#0FFH ; set the WDT period
; enter the STOP mode
; RC-osc WDT running
The RC oscillation period is variable according to the tem-
perature, V_DD and process variations from part to part (ap-
proximately, 120~180uS). The following equation shows
the RC oscillated watchdog timer time-out.
T _{R C W D T} = C L K _{R C} ×2⁸×[W D T R .6~ 0]+ (C L K _{R C} ×2⁸)/2
where, CLK_RC = 120~180uS
In addition, this watchdog timer can be used as a simple 7-
bit timer by interrupt WDTIF. The interval of watchdog
timer interrupt is decided by Basic Interval Timer. Interval
equation is as below.
T_WDT = [WDTR.6~0] × Interval of BIT
Clock Control Register
CKCTLR
-
WAKEUP RCWDT WDTON BTCL
-
0
X
1
X
Watchdog Timer Register
BTS2
X
BTS1
X
BTS0
X
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
WDTR
WDTCL
7-bit Watchdog Counter Register
ADDRESS : EDH
RESET VALUE : 01111111
Bit Manipulation Not Available
WAKEUP
RCWDT
STOP
BTS[2:0]
÷8
÷ 16
3
÷ 32
fxin
÷ 64 ⁸
÷ 128
MUX
0
÷ 256
÷ 512
1
÷ 1024
Internal RC OSC
BTCL
Clear
BITR ( 8-bit )
WDTR (8-bit)
WDTCL WDTON
7-bit Counter
OFD
Overflow Detection
BITIF
Basic Interval Timer
Interrupt
1
CPU RESET
0
Watchdog Timer
Interrupt Request
Figure 20-1 Block Diagram of Watchdog Timer
62
Jan. 2002 ver 2.0