GMS81C1102 Datasheet, PDF (46/89 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C1102 / GMS81C1202
15. Basic Interval Timer
The GMS81C1202 has one 8-bit Basic Interval Timer that
is free-run, can not stop. Block diagram is shown in Figure
15-1 .The 8-bit Basic interval timer register (BITR) is in-
creased every internal count pulse which is divided by
prescaler. Since prescaler has divided ratio by 8 to 1024,
the count rate is 1/8 to 1/1024 of the oscillator frequency.
As the count overflows from FF_H to 00_H, this overflow
causes to generate the Basic interval timer interrupt. The
BITF is interrupt request flag of Basic interval timer.
When write "1" to bit BTCL of CKCTLR, BITR register is
cleared to "0" and restart to count-up. The bit BTCL be-
comes "0" after one machine cycle by hardware.
If the STOP instruction executed after writing "1" to bit
WAKEUP of CKCTLR, it goes into the wake-up timer
mode. In this mode, all of the block is halted except the os-
cillator, prescaler ( only fxin÷2048 ) and Timer0.
If the STOP instruction executed after writing "1" to bit
RCWDT of CKCTLR, it goes into the internal RC oscillat-
ed watchdog timer mode. In this mode, all of the block is
halted except the internal RC oscillator, Basic Interval
Timer and Watchdog Timer. More detail informations are
explained in Power Saving Function. The bit WDTON de-
cides Watchdog Timer or the normal 7-bit timer
Note: All control bits of Basic interval timer are in CKCTLR
register which is located at same address of BITR
(address EC_H). Address EC_H is read as BITR, writ-
ten to CKCTLR. Therefore, the CKCTLR can not be
accessed by bit manipulation instruction.
.
WAKEUP
RCWDT
STOP
BTS[2:0]
÷8
÷ 16
3
÷ 32
fxin
÷ 64
÷ 128
8
MUX
0
÷ 256
÷ 512
1
÷ 1024
Internal RC OSC
BTCL
Clear
BITR (8BIT)
BITIF
To Watchdog Timer
Basic Interval Timer
Interrupt
Figure 15-1 Block Diagram of Basic Interval Timer
Clock Control Register
CKCTLR
-
WAKEUP RCWDT WDTON BTCL BTS2
Symbol
WAKEUP
RCWDT
WDTON
BTCL
Function Description
1: Enables Wake-up Timer
0: Disables Wake-up Timer
1: Enables Internal RC Watchdog Timer
0: Disables Internal RC Watchdog Time
1: Enables Watchdog Timer
0: Operates as a 7-bit Timer
1: BITR is cleared and BTCL becomes "0" automatically
after one machine cycle, and BITR continue to count-up
BTS1 BTS0
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
Basic Interval Timer Clock Selection
000 : fxin ÷ 8
001 : fxin ÷ 16
010 : fxin ÷ 32
011 : fxin ÷ 64
100 : fxin ÷ 128
101 : fxin ÷ 256
110 : fxin ÷ 512
111 : fxin ÷ 1024
Figure 15-2 CKCTLR : Clock Control Register
Jan. 2002 ver 2.0
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